CN-115832009-B - LDMOS structure, design layout and manufacturing method thereof

Abstract

The LDMOS structure comprises a semiconductor substrate, a buried layer of a first doping type, a well region of a second doping type, a drain region of the first doping type, and a buried layer, wherein the buried layer of the first doping type is located in the semiconductor substrate, the drain region of the first doping type is located in the buried layer, the drain region of the first doping type is fully surrounded by the well region, the buried layer is located in the drain region in a direction parallel to a channel of the LDMOS structure, the buried layer is divided into two parts by an undoped buried region, and the undoped buried region is respectively flush with the inner side of the drain region in a direction perpendicular to the channel of the LDMOS structure. The invention can effectively improve BV of the device and improve the quality of the semiconductor device.

Inventors

• DUAN WENTING

Assignees

• 上海华虹宏力半导体制造有限公司

Dates

Publication Date

20260505

Application Date

20221207

Claims (13)

1. 1. An LDMOS structure, comprising: a semiconductor substrate; A buried layer of a first doping type located within the semiconductor substrate; The well region of the second doping type is positioned in the buried layer; the drain region of the first doping type is completely surrounded by the well region and is positioned in the buried layer; the buried layer in the drain region is divided into two parts by an undoped buried region in a direction parallel to a channel direction of the LDMOS structure; and in the direction perpendicular to the channel of the LDMOS structure, the undoped buried regions are respectively flush with the inner side of the drain region.
2. 2. The LDMOS structure of claim 1, wherein the undoped buried region is in contact with and not coincident with the well region.
3. 3. The LDMOS structure of claim 1, wherein the cross-sectional shape of the drain region is a rectangular frame shape, and the extending directions of the two opposite rectangular frames are parallel to the channel direction of the LDMOS structure, denoted as a first drain region; the undoped buried region is flush with the inner side of the first drain region.
4. 4. The LDMOS structure of claim 3 wherein a rectangular border of the other two rectangular borders of the drain region adjacent to the channel of the LDMOS structure is denoted as a second drain region; the distance between the undoped buried region and the second drain region is smaller than or equal to a preset distance so as to enlarge the size of the undoped buried region and reduce the contact between the well region and the buried region.
5. 5. The LDMOS structure of claim 1 wherein the first doping type is N-type and the second doping type is P-type.
6. 6. The LDMOS structure of claim 1, wherein the dopant ions of the well region of the second doping type are boron ions; the doping parameters of the well region of the second doping type meet one or more of the following: The doping amount of the well region with the second doping type is selected from 5e 11-5 e12cm -2 ; the doping depth of the well region with the second doping type is selected from 0.5-2 um.
7. 7. The LDMOS structure of claim 1, further comprising: The grid structure is positioned on the surface of the semiconductor substrate; wherein the undoped buried region is located under a portion of the gate structure.
8. 8. Design layout of an LDMOS structure as claimed in any of claims 1 to 7, comprising: A buried layer layout including buried layer patterns; The well region layout comprises a well region graph, and the well region graph is positioned in the buried layer graph; the drain region layout comprises drain region patterns which are positioned in the buried layer patterns and fully surround the well region patterns; the buried layer patterns in the drain region patterns are separated into two parts by undoped buried region patterns in the direction parallel to the channel direction of the LDMOS structure; and in the direction perpendicular to the channel of the LDMOS structure, the undoped buried region patterns are respectively flush with the inner side of the drain region patterns.
9. 9. The LDMOS structure design layout of claim 8 wherein said undoped buried region pattern is in contact with and non-coincident with said well region pattern.
10. 10. The LDMOS structure design layout of claim 8 wherein the cross-sectional shape of said drain region pattern is a rectangular frame, and the directions of extension of the opposing two rectangular frames are parallel to the channel direction of said LDMOS structure, denoted as a first drain region pattern; the undoped buried region pattern is flush with the inner side of the first drain region pattern.
11. 11. The LDMOS structure design layout of claim 10 wherein a rectangular border of the channel adjacent to the LDMOS structure of the other two rectangular borders of the drain pattern is denoted as a second drain pattern; The distance between the undoped buried region pattern and the second drain region pattern is smaller than or equal to a preset distance so as to enlarge the size of the undoped buried region and reduce the contact between the well region and the buried region.
12. 12. The LDMOS structure design layout of claim 8, further comprising: a gate structure layout including a gate structure pattern; the undoped buried region pattern is located in a region covered by a part of the gate structure pattern.
13. 13. A method of manufacturing an LDMOS structure as claimed in any of claims 1 to 7, comprising: providing a semiconductor substrate; Forming a buried layer of a first doping type in the semiconductor substrate; forming a well region of a second doping type in the buried layer; Forming a drain region of the first doping type fully surrounding the well region in the buried layer; the buried layer in the drain region is divided into two parts by an undoped buried region in a direction parallel to a channel direction of the LDMOS structure; and in the direction perpendicular to the channel of the LDMOS structure, the undoped buried regions are respectively flush with the inner side of the drain region.

Description

LDMOS structure, design layout and manufacturing method thereof Technical Field The invention relates to the technical field of semiconductor manufacturing, in particular to an LDMOS structure, a design layout and a manufacturing method thereof. Background With the rapid development of the semiconductor industry, power integrated circuits (Power Integrated Circuit, PIC) are being used in various fields, such as motor control, flat panel display drive control, drive control of computer peripherals, and so on. Among various power devices, a lateral double-diffused metal oxide semiconductor field effect transistor (Lateral Double Diffused MOSFET, LDMOS) device is taken as an example, and has the characteristics of high working voltage, simple process, easy compatibility with a low-voltage complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) circuit, and the like, so that the device is widely paid attention to. However, in the prior art, the breakdown voltage (breakdown voltage, BV) of the semiconductor device including the LDMOS needs to be increased. Disclosure of Invention The technical problem solved by the invention is to provide an LDMOS structure, a design layout and a manufacturing method thereof, which can effectively improve BV of a device and improve the quality of a semiconductor device. In order to solve the technical problems, the embodiment of the invention provides an LDMOS structure, which comprises a semiconductor substrate, a buried layer of a first doping type, a well region of a second doping type, a drain region of the first doping type, which is fully surrounded by the well region, and is positioned in the buried layer, wherein the buried layer in the drain region is divided into two parts by an undoped buried region in a channel direction parallel to the LDMOS structure, and the undoped buried region is respectively flush with the inner side of the drain region in a channel direction perpendicular to the LDMOS structure. Optionally, the undoped buried region is in contact with the well region and is not coincident. Optionally, the cross section of the drain region is rectangular frame-shaped, and the extending directions of the two opposite rectangular frames are parallel to the channel direction of the LDMOS structure and are marked as a first drain region, wherein the undoped buried region is flush with the inner side of the first drain region. Optionally, a rectangular frame adjacent to the channel of the LDMOS structure in the other two rectangular frames of the drain region is denoted as a second drain region, and a distance between the undoped buried region and the second drain region is smaller than or equal to a preset distance. Optionally, the first doping type is N-type, and the second doping type is P-type. Optionally, the doping ions of the well region with the second doping type are boron ions, and the doping parameters of the well region with the second doping type meet one or more of the following conditions that the doping amount of the well region with the second doping type is selected from 5e 11-5 e12cm -2, and the doping depth of the well region with the second doping type is selected from 0.5-2 um. Optionally, the LDMOS structure further comprises a gate structure positioned on the surface of the semiconductor substrate, wherein the undoped buried region is positioned below a part of the gate structure. In order to solve the technical problems, the embodiment of the invention provides a design layout of an LDMOS structure, which comprises a buried layer layout comprising buried layer patterns, a well region layout comprising well region patterns, a drain region layout comprising drain region patterns, wherein the well region patterns are positioned in the buried layer patterns, the drain region layout comprises drain region patterns which are positioned in the buried layer patterns and fully surround the well region patterns, the buried layer patterns positioned in the drain region patterns are divided into two parts by undoped buried region patterns in a channel direction parallel to the LDMOS structure, and the undoped buried region patterns are respectively flush with the inner sides of the drain region patterns in the channel direction perpendicular to the LDMOS structure. Optionally, the undoped buried region pattern is in contact with the well region pattern and does not coincide. Optionally, the cross section of the drain region pattern is rectangular frame, and the extending directions of the two opposite rectangular frames are parallel to the channel direction of the LDMOS structure and are recorded as a first drain region pattern, wherein the undoped buried region pattern is flush with the inner side of the first drain region pattern. Optionally, a rectangular frame adjacent to the channel of the LDMOS structure in the other two rectangular frames of the drain region pattern is marked as a second drain region pattern, and