CN-115840531-B - Data cache writing method and system of SSD, flash memory controller and SSD controller

CN115840531BCN 115840531 BCN115840531 BCN 115840531BCN-115840531-B

Abstract

The application provides a data cache writing method and system of an SSD, a flash memory controller and an SSD controller, wherein the method comprises the following steps of obtaining data to be written; the method comprises the steps of distributing at least one first buffer unit and/or at least one second buffer unit for data to be written according to a preset proportion, wherein the first buffer unit is from an on-chip SRAM, the second buffer unit is from an off-chip DDR, writing the data to be written into the distributed first buffer unit and/or second buffer unit, and transferring the data cached in the first buffer unit and/or the second buffer unit of the written data to NAND. According to the application, the on-chip SRAM and the off-chip DDR respectively provide a certain proportion of buffer units for buffering the data to be written in, and the buffered data is transferred to the flash memory, so that the average bandwidth of the SSD when transferring the data to the buffer units is improved, and the performance of the SSD is further improved.

Inventors

ZHANG ZHIQING
ZHANG TAILE
YUAN RONG
HUA RONG
XU SIYUAN
SUN QINGTAO

Assignees

苏州启恒融智信息科技有限公司

Dates

Publication Date: 20260512
Application Date: 20220905

Claims (11)

1. The data caching and writing method of the SSD is characterized by comprising the following steps of: Acquiring data to be written; Distributing at least one first buffer unit and at least one second buffer unit for data to be written according to a preset proportion, wherein the first buffer unit is from an on-chip SRAM, and the second buffer unit is from an off-chip DDR; Writing the data to be written into the allocated first cache unit and second cache unit; Transferring the data buffered in the first buffer unit and the second buffer unit to the NAND; transferring the data buffered in the first buffer unit and the second buffer unit to the NAND includes: forming a buffer unit group by the first buffer unit and the second buffer unit of the written data; transferring data cached by the cache unit group to NAND; the cache unit group comprises an off-chip DDR and two on-chip SRAMs; When the first cache unit and the second cache unit form a cache unit group, a plurality of cache unit groups are formed together, and the off-chip DDR (double data rate) of the cache unit groups in different cache unit groups are different, so that the on-chip SRAM (static random Access memory) of the cache unit groups is the same.
2. The data cache writing method of an SSD of claim 1, wherein after transferring the data cached in the first cache unit and the second cache unit to the NAND, further comprising: And responding to the completion of data transfer of a certain buffer memory unit, releasing the buffer memory unit with the completed data transfer, wherein the released buffer memory unit is used for reassigning and receiving new data to be written of the host, and the certain buffer memory unit is a first buffer memory unit or a second buffer memory unit.
3. The data cache writing method of the SSD of claim 1, wherein the cache cell group transfers data in order of transferring data and sequentially releases the cache cells in order of transferring data, wherein the order of transferring data is an order in which the first cache cells or the second cache cells are assembled or an order in which reverse order is sequentially transferred to the NAND.
4. The method according to claim 1, wherein when transferring the data buffered by the buffer unit group to the NAND, the data of the first buffer unit is transferred first, and then the data of the second buffer unit is transferred.
5. The method of claim 1, wherein the size of the cache cell group is equal to the size of the NAND programming cell.
6. The method of claim 1, wherein allocating at least one first buffer unit and at least one second buffer unit for data to be written comprises: And identifying the proportion of the first buffer units allocated from the on-chip SRAM, judging whether the proportion of the first buffer units exceeds a target threshold value, if so, allocating the second buffer units from the off-chip DDR, otherwise, allocating the first buffer units from the on-chip SRAM.
7. The method of claim 6, wherein the first buffer unit is a virtual buffer unit provided by an on-chip SRAM and the second buffer unit is a virtual buffer unit provided by an off-chip DDR.
8. The method according to any one of claims 2 to 7, wherein when the first buffer unit and the second buffer unit for writing data are formed into a buffer unit group, the second buffer unit provided by the off-chip DDR in the different buffer unit group has a duty ratio in a range of 40% -60%.
9. A flash memory controller, wherein the flash memory controller is configured to transfer data buffered in a first buffer unit and a second buffer unit to NAND, wherein the data buffered in the first buffer unit and the second buffer unit are data buffered by allocating data to be written to at least one first buffer unit and at least one second buffer unit according to a predetermined ratio, wherein the first buffer unit is from an on-chip SRAM, and the second buffer unit is from an off-chip DDR; transferring the data buffered in the first buffer unit and the second buffer unit to the NAND includes: forming a buffer unit group by the first buffer unit and the second buffer unit of the written data; transferring data cached by the cache unit group to NAND; the cache unit group comprises an off-chip DDR and two on-chip SRAMs; When the first cache unit and the second cache unit form a cache unit group, a plurality of cache unit groups are formed together, and the off-chip DDR (double data rate) of the cache unit groups in different cache unit groups are different, so that the on-chip SRAM (static random Access memory) of the cache unit groups is the same.
10. An SSD controller, comprising: PCIe interfaces, on-chip SRAM and flash controllers; the PCIe interface is in communication connection with the host, and is used for receiving data to be written from the host, distributing the data to be written to at least one first cache unit and at least one second cache unit according to a preset proportion, wherein the first cache unit is from an on-chip SRAM, and the second cache unit is from an off-chip DDR; One end of the on-chip SRAM is in communication connection with the PCIe interface, the other end of the on-chip SRAM is in communication connection with the flash memory controller, and the on-chip SRAM is used for writing data distributed to the first cache unit; The flash memory controller is used for transferring the data cached in the first cache unit and the second cache unit to NAND; transferring the data buffered in the first buffer unit and the second buffer unit to the NAND includes: forming a buffer unit group by the first buffer unit and the second buffer unit of the written data; transferring data cached by the cache unit group to NAND; the cache unit group comprises an off-chip DDR and two on-chip SRAMs; When the first cache unit and the second cache unit form a cache unit group, a plurality of cache unit groups are formed together, and the off-chip DDR (double data rate) of the cache unit groups in different cache unit groups are different, so that the on-chip SRAM (static random Access memory) of the cache unit groups is the same.
11. A data cache writing system for an SSD, for performing the method of any one of claims 1-7, the system comprising: the SSD controller comprises a PCIe interface, an on-chip SRAM and a flash memory controller; the SSD controller is in communication connection with the host through the PCIe interface, one end of the off-chip DDR and one end of the on-chip SRAM are both in communication connection with the PCIe interface, the other ends of the off-chip DDR and the on-chip SRAM are both in communication connection with the flash memory controller, and the flash memory controller is in communication connection with the NAND; the PCIe interface is used for receiving data to be written from the host, distributing the data to be written to at least one first buffer memory unit and at least one second buffer memory unit according to a preset proportion, wherein the first buffer memory unit is from an on-chip SRAM, and the second buffer memory unit is from an off-chip DDR; The on-chip SRAM is used for writing data distributed to the first cache unit; The flash memory controller is used for transferring the data cached in the first cache unit and the second cache unit to NAND; The off-chip DDR is configured to write data allocated to the second cache unit.

Description

Data cache writing method and system of SSD, flash memory controller and SSD controller Technical Field The present application relates to the field of computer technologies, and in particular, to a method and a system for writing data into an SSD, a flash memory controller, and an SSD controller. Background In the application context of PCIe Gen4, PCIe Gen5, SSD performance requirements are also multiplying, DDR (double rate synchronous dynamic random access memory) being a Buffer (data cache) unit of SSD. As shown in fig. 1, a schematic diagram of a caching method using DDR as a caching unit during data writing in the prior art has some additional overhead, such as query modification of FTL table, data protection bits PI (Protection Information), etc., and performance bottleneck will occur in DDR media, which cannot meet new service performance requirements. For PCIe Gen 4/PCIe Gen5 or higher bandwidth host interfaces that come in the future, SSD receive host data cache space can only be accommodated by SRAM (static random access memory) within the controller chip. Fig. 2 is a schematic diagram of a caching method in which an SRAM in a controller chip is used as a caching unit for data writing in the prior art. The bandwidth performance of on-chip SRAM is typically quite plentiful (SRAM bandwidth is typically tens of times that of off-chip DDR memory), but for cost reasons SRAM capacity is quite limited (typically MB-level, while off-chip DDR can reach GB-level). Under the requirement of SSD concurrency, if the SRAM alone receives the huge pressure of bidirectional data transmission of the uplink and the downlink channels of the data cache, under the limited SRAM capacity, enough data cache space can not be provided to accommodate all read-write data, thereby also causing the limit of SSD performance. In the prior art, hierarchical caching techniques are typically used to balance the contradiction between memory bandwidth and capacity. However, the hierarchical caching technique introduces additional data transfer between different levels of caches, which also consumes bandwidth inside the controller, increasing SSD power consumption and complexity. Therefore, the technical problem to be solved is how to improve the average bandwidth when the SSD transfers data to the cache unit and improve the SSD performance. Disclosure of Invention The application aims to provide a data cache writing method and system of an SSD, a flash memory controller and an SSD controller, which solve the problem of how to improve the average bandwidth when the SSD transfers data to a cache unit. According to a first aspect of the application, the application provides a data caching and writing method of an SSD, which comprises the steps of obtaining data to be written, distributing at least one first caching unit and/or at least one second caching unit for the data to be written according to a preset proportion, wherein the first caching unit is from an on-chip SRAM, the second caching unit is from an off-chip DDR, writing the data to be written into the distributed first caching unit and/or second caching unit, and transferring the data cached in the first caching unit and/or the second caching unit to a NAND. In the data cache writing method of the SSD as described above, in one embodiment, transferring the data cached in the first cache unit and/or the second cache unit to the NAND includes: Forming a buffer unit group by the first buffer unit and/or the second buffer unit of the written data; and transferring the data cached by the cache unit group to NAND. In one embodiment of the data cache writing method of the SSD as described above, after transferring the data cached in the first cache unit and/or the second cache unit to the NAND, the method further includes: and in response to the completion of data transfer of a certain cache unit, releasing the cache unit with the completed data transfer, wherein the released cache unit is used for reassigning and receiving new data to be written by the host. In the data cache writing method of the SSD as described above, in one embodiment, the cache unit group transfers data in the order of transferring data, and sequentially releases the cache units in the order of transferring data, wherein the order of transferring data is the order in which the respective cache units are assembled or the order in which the respective cache units are sequentially directed to the NAND. In the data cache writing method of the SSD as described above, in one embodiment, when transferring the data cached by the cache unit group to the NAND, the data of the first cache unit is transferred first, and then the data of the second cache unit is transferred. In one embodiment, the size of the cache cell group is equal to the size of the NAND programming cell. In the data cache writing method of the SSD described above, in one embodiment, the cache unit group includes one off-chip DDR and two on-chip SRAMs. I