CN-115840717-B - Storage system and method for reading and writing data thereof

CN115840717BCN 115840717 BCN115840717 BCN 115840717BCN-115840717-B

Abstract

The invention discloses a storage system and a method for reading and writing data thereof, wherein the storage system comprises m write interfaces, n read interfaces, a physical storage unit, an entry storage unit, a data moving unit and a read request processing unit, the entry storage unit comprises an idle address list and D storage spaces, each storage space corresponds to one storage address and an address valid bit, and the idle address list records a storage address with invalid address valid bit; the data transfer unit comprises a queue scheduling unit and a transfer request queue, wherein the queue scheduling unit schedules the transfer request queue to store data in the physical storage unit, and the read request processing unit respectively acquires the data in the entry storage unit and the physical storage unit according to the read address in the read request, combines the data and outputs the data. The invention can effectively save the area and the power consumption, thereby reducing the cost and the power consumption of chip design.

Inventors

GENG LEI
XIA JIE
Pu Shenglong

Assignees

南京盛科通信有限公司

Dates

Publication Date: 20260505
Application Date: 20210918

Claims (9)

1. A storage system, the storage system comprising: m write interfaces and n read interfaces; The physical storage unit comprises Z basic storage units, wherein each basic storage unit is an nR1W memory with depth of X/Z and width of Y, X is the depth of a storage system, and Y is the width of the storage system; The access storage unit comprises an idle address list and D storage spaces for storing writing request information, wherein each storage space corresponds to one storage address and an address valid bit for marking whether the storage address is valid, the idle address list is used for recording the storage address of which the address valid bit is invalid, the writing request information comprises a writing address and writing data, the depth D (m-1) X (X/Z) +mxG of the access storage unit is an integer greater than 1, and G is the minimum delay from inputting a writing request to writing the data in the writing request to the physical storage unit; The data transfer unit is connected between the entrance storage unit and the physical storage unit and comprises a queue scheduling unit and Z transfer request queues for storing data transfer information, each transfer request queue corresponds to one basic storage unit, the queue scheduling unit is used for scheduling the transfer request queues and storing data into the corresponding physical storage units according to the data transfer information stored in the transfer request queues, and the data transfer information comprises a storage address of write data in the entrance storage unit and a storage address of write data in the physical storage unit; And the read request processing unit is connected with each read interface, the inlet storage unit and the physical storage unit and is used for respectively acquiring the data in the inlet storage unit and the physical storage unit according to the read address in the read request, combining the data and outputting the data.
2. The memory system of claim 1, wherein the nR1W memory comprises n 1R1W memories of the same size, the 1R1W memory being a memory having one read interface and one write interface.
3. The storage system according to claim 1, wherein the queue scheduling unit schedules L move request queues at a time, L being less than or equal to Z.
4. The memory system according to claim 1, wherein the queue scheduling unit obtains the corresponding data according to the memory address of the write data in the moving data information in the entry memory unit, obtains the corresponding data according to the memory address of the write data in the moving data information in the physical memory unit, and combines and stores the data in the physical memory unit.
5. A method of writing data based on a storage system according to any one of claims 1 to 4, the method comprising the steps of: s100, receiving a plurality of write requests and judging whether write addresses contained in the plurality of write requests are the same or not; S200, in response to the fact that the write addresses are the same, combining write data contained in a plurality of write requests with the same write addresses, and combining the plurality of write requests with the same write addresses into one write request; S300, judging whether the address valid bit in the entry storage unit is the same valid address as the write address of the current write request stored in the valid storage space; S400, obtaining a storage address of the storage space in response to the existence of the same effective address, combining the data stored by the storage address with the write data in the write request, and storing the combined data into the storage address; S500, calculating a corresponding basic storage unit according to a write address in a write request, and further storing movement information into a movement request queue corresponding to the basic storage unit; S600, the queue scheduling unit schedules the moving request queue and stores the data into the corresponding physical storage unit according to the data moving information stored in the moving request queue.
6. The method of claim 5, wherein the queue scheduling unit schedules L move request queues at a time, L being less than or equal to Z.
7. The method according to claim 5, wherein in step S600, the queue scheduling unit obtains corresponding data according to the storage address of the write data in the moving data information in the entry storage unit, obtains corresponding data according to the storage address of the write data in the moving data information in the physical storage unit, and combines and stores the corresponding data in the physical storage unit.
8. A method of reading data based on the storage system of any one of claims 1-4, comprising: s100, inquiring whether the same write address exists in a storage space with the effective address bit in the storage unit of the entry as the effective address according to the read address contained in the read request; s200, corresponding data are acquired from the entrance storage unit in response to the existence of the same address; s300, acquiring corresponding data from a physical storage unit according to a read address contained in the read request; and S400, merging the data acquired in the steps S300 and S400 and outputting.
9. The method according to claim 8, wherein in step S100, it is checked whether the address stored in the memory space in which the address valid bit in the entry memory location is valid is identical to the read address.

Description

Storage system and method for reading and writing data thereof Technical Field The present invention relates to the field of memory technologies, and in particular, to a memory system and a method for reading and writing data in the memory system. Background The memory is a device for storing programs and various data, and can be classified into an on-chip memory and an off-chip memory according to whether it is on a chip, wherein the on-chip memory is widely used in a large scale integrated circuit design. The on-chip Memory is typically implemented in an SRAM (Static Random-Access Memory) manner, or in a register-built FA (FlopArray, flip-flop array, or register array) manner. Speed and cost are often important grounds for selecting on-chip memory. In high bandwidth network chip designs, multiple read-write port memory is required. The multi-read-write port memory is generally implemented in two ways, namely an FA memory built by a register, and a nRmW memory built by m×n SRAMs with target specifications, wherein the nRmW memory refers to a memory with n read interfaces and m write interfaces. As shown in fig. 1, the FA memory built by the register is schematically structured. According to the figure, a memory array is built through a register, each bit is realized through the register, corresponding read-write control logic is matched, and finally, the data reading and writing are realized. However, compared with the SRAM, the physical area of the register is larger and the power consumption is high, which finally results in relatively high area and power consumption of the multi-read-write port memory. The memory is an important component of the chip, and the memory area and the power consumption increase and the power consumption and the cost of the chip increase. As shown in fig. 2, a schematic diagram of the mRnW memory built by using m×n SRAMs of the target specification is shown. In the mRnW memory, the number of read/write ports determines the number of 1 read/1 write memories required, and if a memory having 9 read ports, 8 write ports, a depth of 16384 and a bit width of 64 needs to be built, 72 memories having 1 read port, 1 write port, a depth of 16384 and a bit width of 64 need to be built. However, this results in a large amount of physical resources being occupied, increasing the cost of the chip. Disclosure of Invention The invention aims to provide a memory system capable of saving cost and power consumption, and a method for reading and writing data by the memory system. To achieve the above object, the present invention proposes a storage system, which: m write interfaces and n read interfaces; The physical storage unit comprises Z basic storage units, wherein each basic storage unit is an nR1W memory with depth of X/Z and width of Y, X is the depth of a storage system, and Y is the width of the storage system; The entry storage unit comprises a free address list and D storage spaces for storing writing request information, each storage space corresponds to one storage address and an address valid bit for marking whether the storage address is valid, the free address list is used for recording the storage address of which the address valid bit is invalid, and the writing request information comprises a writing address and writing data; The data transfer unit is connected between the entrance storage unit and the physical storage unit and comprises a queue scheduling unit and Z transfer request queues for storing data transfer information, each transfer request queue corresponds to one basic storage unit, the queue scheduling unit is used for scheduling the transfer request queues and storing data into the corresponding physical storage units according to the data transfer information stored in the transfer request queues, and the data transfer information comprises a storage address of write data in the entrance storage unit and a storage address of write data in the physical storage unit; And the read request processing unit is connected with each read interface, each access storage unit and each physical storage unit and is used for respectively acquiring data in the access storage unit and the physical storage unit according to a read address in a read request, combining the data in the access storage unit and the data in the physical storage unit and outputting the data, wherein D is more than or equal to (m-1) X (X/Z) +m X G, and m, n, X, Z is an integer larger than 1. Preferably, the nR1W memory includes n 1R1W memories with the same specification, and the 1R1W memory is a memory having one read interface and one write interface. Preferably, the minimum depth of the entry memory cell is (m-1) × (X/Z) +mxg, where G is the minimum latency from inputting a write request to writing data in the write request to the physical memory cell. Preferably, the queue scheduling unit schedules L shift request queues at a time, where L is less than or equal to Z. Preferably, the queue scheduling