CN-115858448-B - Multiprocessor computing device and trusted chain construction method thereof

CN115858448BCN 115858448 BCN115858448 BCN 115858448BCN-115858448-B

Abstract

The embodiment of the specification discloses a multiprocessor computing device and a trusted chain construction method thereof, wherein the computing device comprises more than two processors, the method comprises the steps of starting a first trusted root on the computing device, respectively verifying initial codes of all the processors through the first trusted root and starting initial codes of corresponding processors after verification is passed, verifying next-stage codes of the two or more processors through the initial codes, starting next-stage codes after verification is passed, verifying next-stage codes through the initial codes, starting the next-stage codes after verification is passed, and accordingly verifying next-stage codes layer by layer and completing the trusted chain construction of the processors, wherein information related to verification is stored in the first trusted root.

Inventors

HOU WEIXING
WU PENG
AN WEI
LUO HAILIN
LI CHAO
HU LEI
SHUAI FENGYUN

Assignees

支付宝(杭州)信息技术有限公司

Dates

Publication Date: 20260508
Application Date: 20221220

Claims (10)

1. A method of trusted chain construction for a multiprocessor computing device, the computing device comprising two or more processors, the method comprising: initiating a first root of trust located on the computing device; Respectively verifying the first codes of all the processors through the first trusted root, and starting the first codes of the corresponding processors after the verification is passed; For each of the more than two processors, the initial code verifies the next-stage code and starts the next-stage code after the verification is passed; verifying the next code of the initial code, starting the next code after the verification is passed, and verifying and starting the next code layer by layer according to the verification, so as to complete the establishment of a trusted chain of the processor; Wherein information related to each of the authentications is stored in a first trusted root, a trusted report root of the first trusted root is used to send an audit report to a corresponding requestor in response to a attestation request, the audit report including at least a portion of the information related to each of the authentications, the requestor being a processor in the computing device.
2. The method of claim 1, the first trusted root is based on a secure chip implementation that includes a trusted metrics root, a trusted storage root, and the trusted reporting root.
3. The method according to claim 1 or 2, wherein the first trusted root is used for respectively verifying the head codes of the processors, and the method comprises the steps of measuring one or more pieces of information of the head codes of the processors respectively through a trusted measurement root in the first trusted root, comparing the measurement result with a pre-stored reference value, and determining that the head codes of the corresponding processors pass verification when the comparison result is consistent; For each of the above two processors, the verification includes measuring one or more items of information of the next-stage code according to a preset measuring mechanism through the current-stage code, comparing the measuring result with a pre-stored reference value, and determining that the verification of the next-stage code is passed when the comparison result is consistent.
4. The method of claim 3, wherein the information associated with each of the authentications is stored through a trusted storage root of a first trusted root, and wherein the requestor further comprises a device other than the computing device.
5. The method of claim 1, wherein the two or more processors comprise a main processor and a coprocessor, wherein the first code of the main processor is BIOS; And verifying the next-stage code of the main processor by the initial code and starting the next-stage code after the initial code passes the verification, and verifying and starting the next-stage code layer by layer according to the next-stage code to finish the establishment of a trusted chain of the processor, wherein the method comprises the following steps of: Verifying the main guide code through the BOIS, and calling the main guide code into the memory of the computing equipment to run after the main guide code passes the verification; Verifying the OS loader through the main boot code, and calling the OS loader into the memory of the computing device to operate after the OS loader passes the verification; And verifying the OS kernel program through the OS loader, and calling the OS kernel program into the memory of the computing device to run after the verification is passed.
6. The method of claim 5, wherein the initial code verifies the next level code and starts the next level code after the initial code passes the verification, and the next level code is verified and started layer by layer according to the initial code, so that the establishment of the trusted chain of the processor is completed, and the method further comprises the steps of: one or more applications are verified by the OS kernel and, after verification is passed, the applications are called into the memory of the computing device for execution.
7. The method of claim 1, wherein the two or more processors comprise a main processor and a coprocessor comprising one or more of GPU, DPU, DSA.
8. A multiprocessor computing device includes a first root of trust and two or more processors, wherein, The first trusted root is used for respectively verifying the first codes of the processors after the first trusted root is started, and starting the first codes of the corresponding processors after the first trusted root passes the verification; Each of the two or more processors is used for verifying the next-stage code through the initial code and starting the next-stage code through the initial code after the verification is passed; verifying the next-level code through the next-level code of the initial code, and starting the next-level code through the next-level code of the initial code after the verification is passed; Wherein information related to each of the authentications is stored in a first trusted root, a trusted report root of the first trusted root is used to send an audit report to a corresponding requestor in response to a attestation request, the audit report including at least a portion of the information related to each of the authentications, the requestor being a processor in the computing device.
9. The computing device of claim 8, the first trusted root being based on a secure chip implementation comprising a trusted metrics root, a trusted storage root, and the trusted reporting root; The first credible root is further used for measuring one or more items of information of the initial codes of the processors through the credible measurement root, comparing the measurement result with a pre-stored reference value, and determining that the initial codes of the corresponding processors pass the verification when the comparison result is consistent; in order to realize layer-by-layer verification, each of the two or more processors is further used for measuring one or more pieces of information of the next-stage code through the current-layer code according to a preset measuring mechanism, comparing the measuring result with a pre-stored reference value, and determining that the verification of the next-stage code is passed when the comparison result is consistent.
10. The computing device of claim 8 or 9, wherein the information associated with each of the authentications is stored via a trusted storage root of a first trusted root, and wherein the requestor further comprises a device other than the computing device.

Description

Multiprocessor computing device and trusted chain construction method thereof Technical Field The invention relates to the technical field of information security, in particular to multiprocessor computing equipment and a method for constructing a trusted chain of the multiprocessor computing equipment. Background The trusted computing system constructs a trusted immune architecture of a 'host-trusted double node'. Specifically, a logically independent trusted system is built outside a self-owned system of the computing device (or called host device), and the trusted system can create a trusted chain from bottom software and hardware of the computing device to an application program for the host device when the host device is powered on, so that the host device is fully protected from bottom to top. With the increasing demands of computing performance, there are often two or more processors in a computing device, and thus, how to construct a trusted chain of a multiprocessor computing device, and to provide better security support for the multiprocessor computing device is a technical problem to be solved. Disclosure of Invention One of the embodiments of the present disclosure provides a method for constructing a trusted chain of a multiprocessor computing device, where the computing device includes two or more processors, the method includes starting a first root of trust located on the computing device, verifying a first code of each processor through the first root of trust, and starting a first code of a corresponding processor after verification is passed, verifying a next-level code of each of the two or more processors through the first code, starting a next-level code of each of the two or more processors after verification is passed, verifying a next-level code of each of the first code, starting the next-level code after verification is passed, and accordingly verifying and starting a next-level code layer by layer, thereby completing establishment of the trusted chain of the processor, wherein information related to each of the verifications is stored in the first root of trust. One of the embodiments of the present disclosure provides a multiprocessor computing device, including a first trusted root and two or more processors, where the first trusted root is configured to verify a first code of each processor after a start-up, and to start up a first code of a corresponding processor after a verification pass, and each of the two or more processors is configured to verify a next-stage code thereof by the first code and to start up a next-stage code thereof after the verification pass, verify a next-stage code thereof by the next-stage code of the first code and to start up the next-stage code by the next-stage code of the first code after the verification pass, and in this way, verify and start up a next-stage code layer by layer, thereby completing establishment of a trusted chain of the processor, and where information related to each of the verifications is stored in the first trusted root. Drawings The present specification will be further elucidated by way of example embodiments, which will be described in detail by means of the accompanying drawings. The embodiments are not limiting, in which like numerals represent like structures, wherein: FIG. 1 is an exemplary flow chart of a method of trusted chain building for a multiprocessor computing device, shown in accordance with some embodiments of the present specification; FIG. 2 is a schematic diagram of a computing device shown in accordance with some embodiments of the present description; FIG. 3 is a schematic diagram of a trusted chain of host processors shown in accordance with some embodiments of the present description; Figure 4 is a diagram of an example chain of trust for a coprocessor according to some embodiments of the present description. Detailed Description In order to more clearly illustrate the technical solutions of the embodiments of the present specification, the drawings that are required to be used in the description of the embodiments will be briefly described below. It is apparent that the drawings in the following description are only some examples or embodiments of the present specification, and it is possible for those of ordinary skill in the art to apply the present specification to other similar situations according to the drawings without inventive effort. Unless otherwise apparent from the context of the language or otherwise specified, like reference numerals in the figures refer to like structures or operations. It will be appreciated that "system," "apparatus," "unit" and/or "module" as used herein is one method for distinguishing between different components, elements, parts, portions or assemblies of different levels. However, if other words can achieve the same purpose, the words can be replaced by other expressions. As used in this specification, the terms "a," "an," "the," and/or "the" are not intend