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CN-115876333-B - Infrared detector, control method thereof and preparation method thereof

CN115876333BCN 115876333 BCN115876333 BCN 115876333BCN-115876333-B

Abstract

The embodiment of the application provides an infrared detector, a control method and a preparation method thereof, relates to the technical field of infrared imaging equipment, and aims to solve the problem of high circuit design and manufacturing cost. The infrared detector reading circuit comprises N column reading circuits, a row scanning circuit comprising M sub-scanning circuits and a connecting node array, wherein the connecting node array comprises M multiplied by N pairs of first nodes and second nodes, the first nodes are connected with the column reading circuits through the sub-scanning circuits, the second nodes are connected with a grounding end through the sub-scanning circuits, and the first array comprises a plurality of first pixels which are arranged into P first pixel rows and Q first pixel columns, and M is more than P and/or N is more than Q. And the reading circuit is configured to control the Q column reading circuits connected with the first array to read data in the process of scanning the P first pixel rows line by line. The infrared detector described above may be used for infrared imaging.

Inventors

  • LIU JUN
  • HE JIA
  • ZHANG ZHIYUAN
  • Jiang kangli

Assignees

  • 杭州海康微影传感科技有限公司

Dates

Publication Date
20260505
Application Date
20221202

Claims (20)

  1. 1. An infrared detector, comprising: the reading circuit comprises a column reading circuit, a row scanning circuit and a connecting node array, wherein N columns are corresponding to N columns, the row scanning circuit comprises M sub-scanning circuits corresponding to M rows, the connecting node array comprises M multiplied by N pairs of first nodes and second nodes corresponding to M rows and N columns, the first nodes are connected with the column reading circuit of the column through the sub-scanning circuits of the row, the second nodes are connected with a grounding end through the sub-scanning circuits of the row, and A first array disposed on the readout circuitry, the first array comprising P x Q first pixels arranged in P first pixel rows and Q first pixel columns; Wherein M, N, P and Q are positive integers, and M > P and/or N > Q; One end of a first pixel in the first pixel column is connected with one column readout circuit through the first node and the sub-scanning circuit, and the other end of the first pixel is connected with the grounding end through the second node and the sub-scanning circuit; Q first pixel columns are respectively connected with Q column readout circuits; the readout circuit is configured to control Q column readout circuits connected to the first array to perform data readout and control column readout circuits not connected to the first array to not perform data readout in a process of controlling the row scanning circuit to perform progressive scanning on P first pixel rows in the first array.
  2. 2. The infrared detector of claim 1, wherein M = K 1 ×P,N=K 2 x Q, wherein K 1 and K 2 are positive integers; In the first node of the adjacent K 1 row K 2 column, a first node connected with the first pixel is included; In the second node of the adjacent K 1 row K 2 column, a second node connected with the first pixel is included; The first node and the second node connected to the same first picture element are in different rows and/or different columns of the array of connected nodes.
  3. 3. The infrared detector of claim 2, wherein K 1 and K 2 are both equal to 2.
  4. 4. The infrared detector as set forth in claim 3, wherein in said array of connection nodes, said first node and said second node are each node structures independent of each other; A first node connected with the first pixel (X 1 ,Y 1 ) is A (X A ,Y A ), and a second node connected with the first pixel (X 1 ,Y 1 ) is B (X B ,Y B ); Wherein the first pixel (X 1 ,Y 1 ) is a first pixel in an X 1 row and a Y 1 column in the first array; The first node A (X A ,Y A ) is a first node in the X A row and Y A column in the connected node array; The second node B (X B ,Y B ) is a second node in the X B row and Y B column in the connected node array; And satisfies the following: X A =2×X 1 -1,Y A =2×Y 1 -1; X B =2×X 1 ,Y B =2×Y 1 。
  5. 5. The infrared detector as set forth in claim 3, wherein in the same column of said array of connected nodes, said first node is of the same structure as a second node of an adjacent next row; a first node connected with the first pixel (X 1 ,Y 1 ) is A (X A ,Y A ), and a second node connected with the first pixel (X 1 ,Y 1 ) is B (X B ,Y B ); Wherein the first pixel (X 1 ,Y 1 ) is a first pixel in an X 1 row and a Y 1 column in the first array; The first node A (X A ,Y A ) is a first node in the X A row and Y A column in the connected node array; The second node B (X B ,Y B ) is a second node in the X B row and Y B column in the connected node array; And satisfies the following: X A =2×X 1 -1,Y A =2×Y 1 -1; X B =2×X 1 ,Y B =2×Y 1 -1。
  6. 6. The infrared detector as set forth in any one of claims 1 to 5, wherein the sub-scanning circuit comprises a first row selection switch and a second row selection switch, wherein both ends of the first row selection switch are respectively connected with the first node and a column readout circuit of a column, and both ends of the second row selection switch are respectively connected with the second node and the ground terminal; The line scanning circuit further comprises a time sequence control circuit, wherein the time sequence control circuit is connected with the first line selection switch and the second line selection switch and is configured to scan P first pixel lines in the first array line by controlling the on and off of the first line selection switch and the second line selection switch.
  7. 7. The infrared detector of claim 6, wherein one row of said first pixels corresponds to K adjacent sub-scanning circuits, K being a positive integer greater than 1; the timing control circuit includes: m timing signal receiving terminals configured to receive row selection timing signals for line-by-line scanning of M of the sub-scanning circuits, and The first pixel array comprises P first sub-circuits arranged corresponding to P first pixel rows, wherein one end of each first sub-circuit is connected with a first row selection switch and a second row selection switch which are connected with the first pixel rows, the other end of each first sub-circuit is connected with K time sequence signal receiving ends, and the K time sequence signal receiving ends are parts, corresponding to the first pixel rows, of the M time sequence signal receiving ends; In the case where any one of the K timing signal receiving terminals receives a row selection timing signal, the first sub-circuit is configured to control both of a first row selection switch and a second row selection switch connected to the first sub-circuit to be turned on.
  8. 8. The infrared detector of claim 7, wherein the first sub-circuit comprises an or gate, an output of the or gate is connected to the first row selection switch, and an input of the or gate is connected to the K timing signal receiving terminals.
  9. 9. The infrared detector according to claim 7, wherein the timing control circuit further includes M second sub-circuits provided corresponding to the M sub-scanning circuits, one end of the second sub-circuits being connected to a first row selection switch and a second row selection switch in the sub-scanning circuit, and the other end of the second sub-circuits being connected to a timing signal receiving end corresponding to the sub-scanning circuit; The second sub-circuit is configured to control a first row selection switch and a second row selection switch connected with the second sub-circuit to be conducted when the row selection timing signal is received; The readout circuit further comprises a mode switching circuit, wherein the mode switching circuit comprises a first mode switch and a second mode switch with opposite switch states, the first mode switch is arranged in the first sub-circuit, and the second mode switch is arranged in the second sub-circuit.
  10. 10. The infrared detector as set forth in any one of claims 1 to 5, wherein the column readout circuit comprises a circuit bias circuit, an integrator, and a sample-and-hold circuit connected in this order; The readout circuit further comprises a mode switching circuit, wherein the mode switching circuit comprises a third mode switch, and the third mode switch comprises a first sub-switch and a second sub-switch which are opposite in switch state; In the column readout circuit not connected to the first pixel column, the first sub-switch is disposed between the integrator and the sample-and-hold circuit, and the second sub-switch is disposed between the sample-and-hold circuit and a ground terminal.
  11. 11. The infrared detector according to any one of claims 1 to 5, characterized in that n=2×q; Among the N column readout circuits, the column readout circuits in odd order are connected to a first column of picture elements in the first array.
  12. 12. An infrared detector, comprising: the substrate comprises a reading circuit, wherein the reading circuit comprises a column reading circuit, a row scanning circuit and a connecting node array, N columns of the column reading circuit are arranged corresponding to N columns, the row scanning circuit comprises M sub-scanning circuits corresponding to M rows, the connecting node array comprises M multiplied by N pairs of first nodes and second nodes, the M multiplied by N pairs of first nodes and the second nodes are arranged corresponding to the M rows and the N columns, the first nodes are connected with the column reading circuit of the column through the sub-scanning circuits of the row, and the second nodes are connected with a grounding end through the sub-scanning circuits of the row; A first array on one side of the substrate, the first array comprising P×Q first pixels arranged in P first pixel rows and Q first pixel columns, wherein M, N, P and Q are positive integers, M > P and/or N > Q, and The pixel array comprises a first array, a second array, a connecting bridge pier, Q first pixel columns, Q column readout circuits, a sub-scanning circuit, a grounding terminal, a first pixel array, a second pixel array, a sub-scanning circuit, a grounding terminal, a connecting bridge pier, a first node and a second node, wherein the connecting bridge pier is arranged between the first array and the substrate and is used for connecting the first pixel array and the first node and the second pixel array corresponding to the first pixel array; wherein the readout circuit is configured to control Q of the column readout circuits connected to the first array to perform data readout while controlling the row scanning circuit to perform progressive scanning on P of the first pixel rows in the first array, and control the column readout circuits not connected to the first array to perform no data readout.
  13. 13. The infrared detector of claim 12, wherein M = K 1 ×P,N=K 2 x Q, wherein K 1 and K 2 are positive integers; In the first node of the adjacent K 1 row K 2 column, a first node connected with the first pixel is included; In the second node of the adjacent K 1 row K 2 column, a second node connected with the first pixel is included; the first node and the second node connected with the same first pixel are positioned in different rows and/or different columns of the connected node array; One end of the connecting bridge pier, which is close to the substrate, is connected to a first node and a second node which are connected with the first pixel, and one end of the connecting bridge pier, which is far away from the substrate, is connected with the corresponding first pixel.
  14. 14. The infrared detector of claim 13, wherein K 1 and K 2 are both equal to 2.
  15. 15. The infrared detector of claim 14, wherein in the array of connection nodes, the first node and the second node are each independent node structures; a first node connected with the first pixel (X 1 ,Y 1 ) is A (X A ,Y A ), a second node connected with the first pixel (X 1 ,Y 1 ) is B (X B ,Y B ), and the first node A (X A ,Y A ) and the second node B (X B ,Y B ) are both connected with the connecting bridge pier; Wherein the first pixel (X 1 ,Y 1 ) is a first pixel in an X 1 row and a Y 1 column in the first array; the first node A (X A ,Y A ) is a first node in the X A row and Y A column in the connected node array, and meets X A =2×X 1 -1,Y A =2×Y 1 -1; The second node B (X B ,Y B ) is a second node in row X B , column Y B of the connected node array, and satisfies X B =2×X 1 ,Y B =2×Y 1 .
  16. 16. The infrared detector as set forth in claim 14, wherein in the same column of the connected node array, the first node is of the same structure as a second node of an adjacent next row; A first node connected with the first pixel (X 1 ,Y 1 ) is A (X A ,Y A ), a second node connected with the first pixel (X 1 ,Y 1 ) is B (X B ,Y B ), and the first node A (X A ,Y A ) and the second node B (X B ,Y B ) are both connected with the connecting bridge pier; Wherein the first pixel (X 1 ,Y 1 ) is a first pixel in an X 1 row and a Y 1 column in the first array; the first node A (X A ,Y A ) is a first node in the X A row and Y A column in the connected node array, and meets X A =2×X 1 -1,Y A =2×Y 1 -1; the second node B (X B ,Y B ) is a second node in the connected node array in row X B and column Y B , and satisfies X B =2×X 1 ,Y B =2×Y 1 -1.
  17. 17. The infrared detector according to any one of claims 14 to 16, wherein in the first node and the second node which are not connected to the first pixel, part or all of them are left empty, or part or all of them are provided with insulating bridge piers; and one end of the insulating bridge pier, which is far away from the substrate, supports the first pixel.
  18. 18. A control method of an infrared detector, characterized by being applied to the infrared detector according to any one of claims 1 to 17, comprising: In the process of controlling a line scanning circuit to scan P first pixel lines in a first array line by line, controlling Q column reading circuits connected with the first array to read data, and controlling column reading circuits not connected with the first array to not read data.
  19. 19. The control method according to claim 18, wherein in the infrared detector, m=k 1 ×P,N=K 2 ×q, one first pixel row in the first array corresponds to adjacent K 1 of the sub-scanning circuits, and one first pixel column corresponds to adjacent K 2 column readout circuits, wherein K 1 and K 2 are both positive integers; In the control method, the control line scanning circuit scans P first pixels in the first array line by line, including: receiving row selection time sequence signals for scanning M sub-scanning circuits row by row; controlling the first pixel row to be conducted with the corresponding column readout circuit in K 1 row selection time sequences corresponding to the first pixel row; the controlling the Q column readout circuits connected to the first array to perform data readout and controlling the column readout circuits not connected to the first array not to perform data readout includes: and in the adjacent K 2 column readout circuits corresponding to the first pixel column, controlling the column readout circuits connected with the first pixel column to perform data readout, and controlling the column readout circuits not connected with the first array to not perform data readout.
  20. 20. The control method according to claim 18, wherein in the infrared detector, m=2×p, n=2×q, and among N of the column readout circuits, the column readout circuits in odd order are connected to a first pixel column in the first array; In the control method, the control line scanning circuit scans P first pixels in the first array line by line, including: receiving row selection time sequence signals for scanning M sub-scanning circuits row by row; In 2 row selection time sequences corresponding to the first pixel row, controlling the first pixel row to be conducted with the corresponding column readout circuit; the controlling the Q column readout circuits connected to the first array to perform data readout and controlling the column readout circuits not connected to the first array not to perform data readout includes: And controlling the column readout circuits in odd order to perform data readout, and controlling the column readout circuits in even order not to perform data readout.

Description

Infrared detector, control method thereof and preparation method thereof Technical Field The embodiment of the application relates to the technical field of infrared imaging equipment, in particular to an infrared detector, a control method and a preparation method thereof. Background The infrared detector generally comprises a pixel array and a readout circuit (Readout Integration Circuits, abbreviated as RIOC) connected with the pixel array, wherein the pixel array comprises a plurality of infrared sensing pixels arranged in a plurality of rows and a plurality of columns, the infrared sensing pixels convert illumination or thermal radiation emitted by a target object into self resistance value changes in the working process, the readout circuit amplifies and reads out the resistance value changes, and finally an infrared image is processed and output according to the read-out result. In the pixel array, the actual physical size of each infrared sensing pixel is the pixel size, and the pixel size reflects the response capability of the infrared detector to light to a certain extent, so that the infrared sensing pixel is a representation of the sensitivity of the infrared detector. For example, the larger the pixel size of an infrared sensing pixel, the greater the number of photons that can be received, and the greater the amount of charge that can be generated under the same illumination conditions and exposure time, and thus is more suitable for use in low light or low infrared radiation environments. The smaller the pixel size of the infrared sensing pixels is, the more the number of the pixels in the array area with the same area can be set, the higher the pixel resolution in the array area is, the more obvious the detail signals are, and the infrared sensing pixels are suitable for high-resolution application scenes. The infrared sensing pixels with different pixel sizes can meet different application requirements, but a reading circuit can only adapt to the infrared sensing pixels with one pixel size, and for the infrared sensing pixels with different pixel sizes, different reading circuits are needed to realize data reading, so that the circuit design and manufacturing cost of the reading circuit and the infrared detector are increased. Disclosure of Invention The embodiment of the application provides an infrared detector, a control method and a preparation method thereof, which are used for solving the problem of higher circuit design and manufacturing cost of the infrared detector. In order to achieve the above purpose, the embodiment of the present application adopts the following technical scheme: in one aspect, there is provided an infrared detector including: the reading circuit comprises a column reading circuit, a row scanning circuit and a connecting node array, wherein N columns are corresponding to N columns, the row scanning circuit comprises M sub-scanning circuits corresponding to M rows, the connecting node array comprises M multiplied by N pairs of first nodes and second nodes corresponding to M rows and N columns, the first nodes are connected with the column reading circuit of the column through the sub-scanning circuits of the row, the second nodes are connected with a grounding end through the sub-scanning circuits of the row, and A first array disposed on the readout circuitry, the first array comprising P x Q first pixels arranged in P first pixel rows and Q first pixel columns; wherein M, N, P and Q are positive integers, and M > P and/or N > Q; One end of a first pixel in the first pixel column is connected with one column readout circuit through the first node and the sub-scanning circuit, and the other end of the first pixel is connected with the grounding end through the second node and the sub-scanning circuit; Q first pixel columns are respectively connected with Q column readout circuits; the readout circuit is configured to control Q column readout circuits connected to the first array to perform data readout and control column readout circuits not connected to the first array to not perform data readout in a process of controlling the row scanning circuit to perform progressive scanning on P first pixel rows in the first array. By adopting the infrared detector provided by the embodiment of the application, the first array is arranged on the read-out circuit which is arranged corresponding to the M rows and N columns of pixel arrays, the number of rows of the first array is smaller than M and/or the number of columns of the first array is smaller than N, and the first pixel size in the first array is larger than the pixel size designed by the read-out circuit, so that the limitation that the read-out circuit can only adapt to the infrared sensing pixel of one pixel size is eliminated, and the cost of circuit design and manufacture in the infrared detector can be saved. In some embodiments, m=k 1×P,N＝K2 ×q, where K 1 and K 2 are both positive integers; In the first no