CN-115878554-B - Data transmission circuit and data transmission method based on network on chip

Abstract

The embodiment of the invention discloses a data transmission circuit and a data transmission method based on a network-on-chip. The data buffer zone is used for buffering data to be transmitted, which is received from a data receiving port, and comprises a plurality of data buffer zone units, wherein the data buffer zone is connected with at least two pointer queues, each pointer queue corresponds to one target direction, each pointer queue buffers a pointer of the data to be transmitted, which is sent to the corresponding target direction, and the pointer is a position number of each data buffer zone unit in the data buffer zone, and is used for reading the data to be transmitted from the data buffer zone units of the data buffer zone. By the circuit, the time delay of the circuit in the data transmission process can be reduced, and the resources of a data buffer area can be saved.

Inventors

• HUANG KAI

Assignees

• 北京希姆计算科技有限公司

Dates

Publication Date

20260505

Application Date

20210929

Claims (9)

1. 1. A network-on-chip based data transmission circuit, the circuit comprising: the data buffer area is used for buffering data to be transmitted, which are received from a data receiving port, and comprises a plurality of data buffer area units, and the data buffer area is connected with at least two pointer queues; the direction buffer area comprises a plurality of direction buffer area units, each direction buffer area unit corresponds to the data buffer area unit, and is used for buffering target direction marks of data to be sent of the data buffer area unit, wherein the target direction marks are used for indicating at least one target direction to which the data to be sent need to be sent; Each pointer queue corresponds to one target direction, each pointer queue caches pointers of data to be sent in the corresponding target direction, each pointer queue corresponds to one target direction, and each pointer is cached to at least one corresponding pointer queue according to the target direction mark corresponding to each pointer; the pointer is a position number of each data buffer unit in the data buffer, and is used for reading data to be sent in the data buffer unit of the data buffer.
2. 2. The circuit of claim 1, wherein the pointer queue is a first-in first-out queue.
3. 3. The circuit of claim 2, wherein the direction buffer further comprises a fast look-up circuit for looking up a direction buffer cell in the direction buffer that is empty of the target direction flag, the direction buffer cell that is empty of the target direction flag being used to write the target direction flag of the data to be transmitted newly received by the data buffer.
4. 4. A method for network-on-chip based data transmission, the method comprising: receiving data to be transmitted and a target direction mark of the data to be transmitted; caching the data to be sent to an idle data buffer area unit in a data buffer area, wherein the idle data buffer area unit is arranged at any position of the data buffer area; The target direction marks of the data to be sent are obtained, a first pointer queue is determined from at least two pointer queues according to the target direction marks, pointers of the data to be sent are pushed into the first pointer queue, wherein the pointers are position numbers of data buffer units of the data to be sent in the data buffer, the target direction marks are used for indicating at least one target direction to which the data to be sent needs to be sent, each pointer queue corresponds to one target direction, each pointer queue caches pointers of the data to be sent in the corresponding target direction, and the number of the first pointer queues is one or more.
5. 5. The method of claim 4, wherein the method further comprises: and storing the target direction mark of the data to be sent into a direction buffer area unit corresponding to the data buffer area unit, wherein the direction buffer area unit is an idle unit in a direction buffer area.
6. 6. The method of claim 5, wherein the pointer queue is a first-in-first-out queue, and in response to dequeuing the pointer of the pointer queue, the method further comprises: Acquiring data to be transmitted in a first data buffer unit according to a dequeue pointer, wherein the first data buffer unit is the data buffer unit in the data buffer indicated by the dequeue pointer; and setting a value in a target direction mark corresponding to a second pointer queue in a direction buffer unit corresponding to the first data buffer unit to 0, wherein the second pointer queue is a pointer queue where the dequeued pointer is located.
7. 7. A method as claimed in claim 5 or 6, characterized in that the method further comprises: searching a direction buffer zone unit with the target direction mark being empty in the direction buffer zone; And determining that a second data buffer unit is idle, wherein the second data buffer unit is a data buffer unit corresponding to the direction buffer unit with the target direction marked as empty.
8. 8. An integrated circuit comprising a plurality of cores, a network on chip, and a data transmission circuit according to any of claims 1-3.
9. 9. A board on which the integrated circuit of claim 8 is included.

Description

Data transmission circuit and data transmission method based on network on chip Technical Field The invention relates to the technical field of communication, in particular to a data transmission circuit and a data transmission method based on a network-on-chip. Background Communication between subsystems is implemented in a System on Chip (SoC) using a network-on-Chip (NoC). Specifically, in the NoC architecture, the subsystem (i.e., the computing core) is included, the subsystems are interconnected through a Broadcast Router (BR), each direction of the BR can receive data and transmit data, ports for receiving data are denoted by RX, each BR can receive data from four directions, that is, each BR includes four RX, RX0, RX1, RX2 and RX3, respectively, ports for transmitting data are denoted by TX, each BR can transmit data to four directions, that is, each BR includes four TX, TX0, TX1, TX2 and TX3, respectively, wherein each direction of RX is correspondingly provided with a splitter (splitter) for transmitting data received in the direction to TX in other three directions, each splitter includes a data buffer, and the RX stores received data in the data buffers of the splitters before transmitting data after receiving data. In the prior art, when data received by an RX needs multicasting, when the data enters the data buffer, a plurality of copies are made, the plurality of copies are sequentially arranged in the data buffer, and simultaneously pointers and direction information corresponding to the data needing multicasting are also stored in a pointer queue. When the multicasting is realized, pointers in a pointer queue are required to be searched from beginning to end in sequence, pointers which are arranged at the forefront in each direction are determined to be dequeued at the same time, then corresponding data are read from the data buffer according to the pointers, and the read data are sent to the corresponding TX side according to the direction information, so that the multicasting of the data is realized. When data is sent in only one direction, the pointer queue also needs to be searched for the pointer that is most forward in that direction. Therefore, when multicasting is realized, the data needs to be copied for a plurality of times, resources of a data buffer area are occupied, pointer queues need to be searched from beginning to end each time when dequeuing is carried out, pointers corresponding to each direction are determined, if the depth of the pointer queues is large, the searching mode can cause time delay of a circuit, and the pointers need to be sequentially moved forward for updating after dequeuing each time, and the time delay of the circuit can also be caused. In summary, how to reduce the time delay of the circuit and save the resources of the data buffer during the data transmission process is a problem to be solved at present. Disclosure of Invention In view of this, the embodiment of the invention provides a data transmission circuit and a data transmission method based on a network on chip, which can reduce the time delay of the circuit in the data transmission process and save the resources of a data buffer. In a first aspect, an embodiment of the present invention provides a network-on-chip-based data transmission circuit, including: the data buffer area is used for buffering data to be transmitted, which are received from a data receiving port, and comprises a plurality of data buffer area units, and the data buffer area is connected with at least two pointer queues; Each pointer queue corresponds to one target direction, and each pointer queue caches pointers of data to be sent, which are sent to the corresponding target direction; the pointer is a position number of each data buffer unit in the data buffer, and is used for reading data to be sent in the data buffer unit of the data buffer. Optionally, the circuit further comprises: The direction buffer area comprises a plurality of direction buffer area units, and each direction buffer area unit corresponds to the data buffer area unit and is used for buffering target direction marks of data to be sent of the data buffer area unit. Optionally, the pointer queue is a first-in first-out queue. Optionally, the direction buffer zone further includes a fast search circuit, configured to search a direction buffer zone unit in the direction buffer zone, where the target direction flag is empty, and the direction buffer zone unit in which the target direction flag is empty is used to write the target direction flag of the data to be sent, which is newly received by the data buffer zone. In a second aspect, an embodiment of the present invention provides a method for data transmission based on a network on chip, where the method includes: receiving data to be transmitted; caching the data to be sent to an idle data buffer area unit in a data buffer area, wherein the idle data buffer area unit is arranged at any position of th