CN-115884463-B - Average current control circuit and method

Abstract

Embodiments of the present disclosure relate to average current control circuits and methods. A control circuit includes a flip-flop having an output configured to be coupled to a control terminal of a transistor and to generate a first signal, a comparator having an output coupled to an input of the flip-flop and first and second inputs for receiving the first and second voltages, respectively, a transconductance amplifier having an input for receiving a sense voltage indicative of a current flowing through the transistor and an output coupled to the first input of the comparator, a zero crossing detection ZCD circuit having a first current path terminal configured to be coupled to the transistor and an input of an inductor, wherein the ZCD circuit is configured to detect a demagnetization time of the inductor and to generate a third signal based on the detected demagnetization time, and a reference generator configured to generate the second voltage based on the first signal and the third signal.

Inventors

• C. Adragona
• G. Gritti

Assignees

• 意法半导体股份有限公司

Dates

Publication Date

20260508

Application Date

20220927

Priority Date

20210928

Claims (20)

1. 1. A control circuit, comprising: A driver having an output configured to be coupled to a control terminal of the first transistor; A first flip-flop having a first output coupled to an input of the driver and a first input configured to receive a clock signal, wherein the first flip-flop is configured to generate a first signal at the first output of the first flip-flop; a first comparator having an output coupled to a second input of the first flip-flop, a first input configured to receive a first voltage, and a second input configured to receive a second voltage; A transconductance amplifier having a first input configured to receive a sense voltage indicative of a current flowing through a current path of the first transistor, a second input configured to receive a reference voltage, and an output coupled to the first input of the first comparator; an integrating capacitor coupled to the output of the transconductance amplifier and the first input of the first comparator; a first switch coupled across the integrating capacitor, the first switch having a control terminal configured to receive a second signal, the second signal being an inverted version of the first signal; a zero crossing detection circuit having a first current path terminal configured to be coupled to the first transistor and an input of an inductor, wherein the zero crossing detection circuit is configured to detect a demagnetization time of the inductor based on the input of the zero crossing detection circuit and to generate a third signal based on the detected demagnetization time, and A reference generator configured to generate the second voltage based on the first signal and a third signal.
2. 2. The control circuit of claim 1, wherein the reference generator comprises: An output terminal configured to deliver the second voltage; An averaging capacitor coupled to the output terminal of the reference generator; A second switch having a first terminal configured to receive a first current, a second terminal coupled to the output terminal of the reference generator, and a control terminal configured to receive the first signal; A third switch having a first terminal coupled to the second terminal of the second switch and a second terminal configured to receive the reference voltage and a control terminal configured to be driven based on the third signal, and A first resistor is coupled between the second terminal of the second switch and the first terminal of the third switch.
3. 3. The control circuit of claim 2, wherein the control terminal of the third switch is configured to receive the third signal.
4. 4. The control circuit of claim 2, wherein the reference generator further comprises: An OR gate having an output coupled to the control terminal of the third switch and a first input configured to receive the first signal, and An and gate has a first input configured to receive the second signal, a second input configured to receive the third signal, and an output coupled to the second input of the or gate.
5. 5. The control circuit of claim 2, further comprising a first current generator coupled to the first terminal of the second switch and configured to sink a second current.
6. 6. The control circuit of claim 1, wherein the transconductance amplifier is configured to inject a first current from the output of the transconductance amplifier into the integrating capacitor, the first current being based on the sense voltage, the control circuit further comprising a first current generator configured to inject a second current into the integrating capacitor.
7. 7. The control circuit of claim 1, wherein the zero crossing detection circuit comprises: a first terminal configured to be coupled to the first current path terminal of the first transistor via an interface circuit; a second comparator having a first input coupled to the first terminal and a second input coupled to the first terminal via a low pass filter, and A second flip-flop having a first input configured to receive the second signal, a second input coupled to the output of the second comparator, and an output configured to deliver the third signal.
8. 8. The control circuit of claim 1, further comprising a voltage feed forward circuit comprising a current mirror configured to inject a first current into the first input of the transconductance amplifier based on a second current flowing through an interface circuit coupled to the first current path terminal of the first transistor and the inductor.
9. 9. The control circuit of claim 1, wherein the first input of the first flip-flop corresponds to a set input, and wherein the second input of the first flip-flop corresponds to a reset input.
10. 10. The control circuit of claim 1, wherein the first input of the transconductance amplifier is coupled to a first terminal of a sense resistor having a second terminal configured to receive the reference voltage.
11. 11. The control circuit of claim 1, further comprising a clock circuit having an output coupled to the first input of the first flip-flop.
12. 12. The control circuit of claim 11, wherein the clock circuit comprises: a second switch having a control terminal configured to receive the second signal, a first terminal configured to receive an oscillator current, and a second terminal; a first resistor coupled to the second terminal of the second switch; a second capacitor coupled to the first resistor; A second comparator having a first input coupled to the second terminal of the second switch, a second input, and an output coupled to the first input of the first flip-flop; A third capacitor coupled to the second input of the second comparator; A first current generator coupled to the third capacitor and the second input of the second comparator, and A third switch has a first terminal coupled to the first current generator, a second terminal configured to receive the reference voltage, and a control terminal configured to receive the first signal.
13. 13. The control circuit of claim 1, wherein the clock signal has a fixed frequency.
14. 14. The control circuit of claim 1, wherein the control circuit is integrated in a single integrated circuit.
15. 15. The control circuit of claim 1, wherein the driver is a gate driver, and wherein the first transistor is a power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) or a GaN transistor having a control terminal coupled to the output of the gate driver.
16. 16. A method of controlling current, comprising: Turning on a first transistor based on a clock signal, wherein a current path of the first transistor is coupled to an inductor; generating a sense current based on a current flowing through the current path of the first transistor; integrating the sense current with an integrating capacitor to generate a first voltage; injecting a first current into the averaging capacitor to generate a second voltage; turning off the first transistor when the first voltage becomes higher than the second voltage, and The integrating capacitor is discharged when the first transistor is turned off.
17. 17. The method of claim 16, further comprising generating a sense voltage based on the current flowing through the current path of the first transistor, wherein generating the sense current comprises generating the sense current based on the sense voltage using a transconductance amplifier.
18. 18. The method of claim 16, wherein injecting the first current into the averaging capacitor comprises closing a first switch when the first transistor is turned off and opening the first switch when the first transistor is turned on.
19. 19. The method of claim 18, further comprising: Detecting a demagnetization time of the inductor, and A second switch is controlled based on the detected demagnetization time, the second switch being coupled to the first switch via a first resistor.
20. 20. The method of claim 16, further comprising adjusting an average output current flowing through a load coupled to the inductor based on the first current.

Description

Average current control circuit and method Technical Field The present disclosure relates generally to an electronic system and method, and in particular embodiments to an average current control circuit and method. Background A Light Emitting Diode (LED) driver is configured to provide sufficient current to illuminate the LED. A switching voltage regulator may be used to drive the LEDs. The intensity of light produced by an LED is related to the average current flowing through the LED. In general, the higher the average current flowing through an LED, the higher the intensity of the light produced by the LED. Thus, it is often desirable to drive the LEDs using a current driver to accurately control the average current flowing through the LEDs. By controlling the average current through the LEDs, the LEDs can be dimmed. For example, reducing the intensity of light produced by an LED may be achieved by reducing the average current flowing through the LED. Fluctuations in the average current flowing through the LED may lead to fluctuations in the light emitted by the LED. Thus, the switching converter current driver may be used to properly drive the LEDs by switching at a frequency above the flicker fusion threshold. LED lamp drivers are typically specified for rated output current (sometimes programmable by a user over a range) and output voltage range to power different types/lengths of LED strings. Notably, the rated output current is typically specified with very strict accuracy, typically less than 5% overall. It is also common for LED lamp drivers to provide dimming capability, i.e. to be able to lower the LED current from a nominal value to a low value (sometimes below 1%) so that the user can reduce the intensity of the light output of the LED string. It is generally desirable that the LED current reduction, and hence the light modulation, be seamless and flicker free. Disclosure of Invention According to an embodiment, a control circuit includes a driver having an output configured to be coupled to a control terminal of a first transistor, a first flip-flop having a first output coupled to an input of the driver and a first input configured to receive a clock signal, wherein the first flip-flop is configured to generate a first signal at the first output of the first flip-flop, a first comparator having an output coupled to a second input of the first flip-flop, a first input configured to receive a first voltage, and a second input configured to receive a second voltage, a transconductance amplifier having a first input configured to receive a sense voltage indicative of a current flowing through a current path of the first transistor, a second input configured to receive a reference voltage, and an output coupled to the first input of the first comparator, a first switch coupled across the integrating capacitor, the first switch having a control terminal configured to receive a second signal, the second signal being an inverting signal, the first switch having a zero crossing time detector circuit configured to generate a zero crossing time signal based on the first input and a zero crossing time detector circuit, wherein the first input is configured to generate a zero crossing time detector signal based on the first input and the zero crossing time detector circuit. According to an embodiment, a method includes turning on a first transistor based on a clock signal, wherein a current path of the first transistor is coupled to an inductor, generating a sense current based on a current flowing through the current path of the first transistor, integrating the sense current with an integrating capacitor to generate a first voltage, injecting the first current into an averaging capacitor to generate a second voltage, turning off the first transistor when the first voltage becomes higher than the second voltage, and discharging the integrating capacitor when the first transistor is turned off. According to an embodiment, a switching converter includes a power transistor, a sense resistor coupled to a current path of the power transistor, an inductor coupled to the current path of the power transistor, a driver having an output coupled to a control terminal of the power transistor, a flip-flop having a first output coupled to an input of the driver and a first input configured to receive a clock signal, wherein the flip-flop is configured to generate a first signal at the first output of the flip-flop and wherein the flip-flop is configured to cause the power transistor to turn on based on the clock signal using the first signal, a first comparator having an output coupled to a second input of the flip-flop, the first input configured to receive a first voltage, and a second input configured to receive a second voltage, wherein the flip-flop is configured to cause the power transistor to turn off based on the output of the first comparator using the first signal, a transconductance amplifier having a fir