CN-115910162-B - Delay reduction in SPI flash memory devices

Abstract

The invention relates to latency reduction in SPI flash memory devices. A method may include the steps of receiving a read request from a host device in a memory device, the host device coupled to the memory device through an interface, decoding an address of the read request received from the interface, decoding a command of the read request to determine whether the read request is directed to an aligned address operation, maintaining the decoded address without modification regardless of an actual alignment of the decoded address when the read request is determined to be directed to the aligned address operation, and executing the read request on the memory device in accordance with the aligned address operation by using the decoded address.

Inventors

• G intrater

Assignees

• 对话半导体美国公司

Dates

Publication Date

20260512

Application Date

20211011

Priority Date

20210811

Claims (18)

1. 1. A method, the method comprising the steps of: a) Receiving a read request in a memory device from a host device, the host device coupled to the memory device through an interface; b) Decoding an address of the read request received from the interface; c) Decoding a command of the read request to determine whether the read request is for an aligned address operation; d) When the read request is determined to operate on the aligned address, the decoded address is maintained without modification regardless of the actual alignment of the decoded address; e) Executing the read request on the memory device in accordance with the aligned address operation by using the decoded address, F) Accessing configuration bits on the memory device, and G) The holding step and the executing step are performed only when the configuration bit is in a first state and the read request is determined to operate for the aligned address.
2. 2. The method of claim 1, wherein the aligned address operation is a double word aligned DWA read operation.
3. 3. The method of claim 1, further comprising the step of: a) When the configuration bit is in the second state and the read request is for the aligned address operation, clearing a predetermined number of least significant bits LSB from the decoded address to form a modified address, and B) The read request is performed on the memory device in accordance with the aligned address operation using the modified address when the configuration bit is in the second state.
4. 4. The method of claim 1, wherein, A) The memory device includes a nonvolatile memory, and B) The interface includes a serial interface.
5. 5. The method of claim 1, wherein decoding the command of the read request to determine whether the read request operates on the aligned address comprises matching an opcode with a predetermined opcode.
6. 6. The method of claim 1, wherein the read latency of the aligned address operation is less than a read latency of an operation without address restriction.
7. 7. The method of claim 1, wherein the aligned address operation is a single byte read operation.
8. 8. The method of claim 1, wherein the aligned address operation is a single aligned word read operation.
9. 9. The method of claim 1, wherein the host device is configured to ensure that a starting address is aligned for direct memory access, DMA, that includes the aligned address operation.
10. 10. A memory device comprising a status register having configuration bits, the memory device configured to: a) Receiving a read request from a host device through an interface; b) Decoding the address of the read request; c) Decoding a command of the read request to determine whether the read request is for an aligned address operation; d) When the read request is determined to operate on the aligned address, maintaining the decoded address without modification, regardless of the actual alignment of the decoded address, and E) Executing the read request on the memory device in accordance with the aligned address operation by using the decoded address, Wherein the decoded address is maintained and the read request is performed using the decoded address only when the configuration bit is in the first state and the read request is determined to operate on the aligned address.
11. 11. The memory device of claim 10, wherein the aligned address operation is a double word aligned DWA read operation.
12. 12. The memory device of claim 10, wherein, A) When the configuration bit is in the second state and the read request is for the aligned address operation, clearing a predetermined number of least significant bits LSB from the decoded address to form a modified address, and B) The read request is performed on the memory device in accordance with the aligned address operation using the modified address when the configuration bit is in the second state.
13. 13. The memory device of claim 10, comprising a non-volatile memory, and wherein the interface comprises a serial interface.
14. 14. The memory device of claim 10, wherein the command of the read request is decoded to determine whether the read request is to operate on the aligned address by matching an opcode with a predetermined opcode.
15. 15. The memory device of claim 10, wherein the read latency of the aligned address operation is less than a read latency of an operation without address restriction.
16. 16. The memory device of claim 10, wherein the aligned address operation is a single byte read operation.
17. 17. The memory device of claim 10, wherein the aligned address operation is a single aligned word read operation.
18. 18. The memory device of claim 10, wherein the host device is configured to ensure that a starting address is aligned for direct memory access, DMA, that includes the aligned address operation.

Description

Delay reduction in SPI flash memory devices Technical Field The present invention relates generally to the field of semiconductor devices. More particularly, embodiments of the present invention relate to memory devices, including both volatile memory devices and non-volatile memory devices (such as flash memory devices). Background Nonvolatile memory (NVM) is increasingly found in applications such as solid state hard drives, removable digital picture cards, automotive electronics, household appliances, and the like. Flash memory is the primary NVM technology in use today. However, flash memory has limitations such as relatively high power and relatively low operating speed. Microprocessor performance is very sensitive to memory latency. Many non-volatile memory devices have a relatively slow access time (ACCESS TIME) or delay compared to microprocessors. In addition, many implementations of various communication protocols between microprocessors/hosts and memory, such as Serial Peripheral Interfaces (SPI), can add even more latency than is required by the memory array itself. Disclosure of Invention One aspect of the present invention provides a method comprising the steps of a) receiving a read request from a host device in a memory device, the host device being coupled to the memory device through an interface, b) decoding an address of the read request received from the interface, c) decoding a command of the read request to determine whether the read request is operating for an aligned address, d) maintaining the decoded address without modification regardless of the actual alignment of the decoded address when the read request is determined to be operating for the aligned address, and e) executing the read request on the memory device in accordance with the aligned address operation by using the decoded address. Another aspect of the invention provides a memory device configured to a) receive a read request from a host device over an interface, b) decode an address of the read request, c) decode a command of the read request to determine whether the read request is directed to an aligned address operation, d) maintain the decoded address without modification regardless of an actual alignment of the decoded address when the read request is determined to be directed to the aligned address operation, and e) execute the read request on the memory device in accordance with the aligned address operation by using the decoded address. Drawings FIG. 1 is a schematic block diagram of an example host and memory device arrangement according to an embodiment of the invention. FIG. 2 is a schematic block diagram of an example memory controller system according to an embodiment of the invention. FIG. 3 is a schematic block diagram of an example memory device according to an embodiment of the present invention. FIG. 4 is a schematic block diagram of an example memory device with read request modification control in accordance with an embodiment of the present invention. FIG. 5 is a timing diagram of an example read access according to an embodiment of the invention. FIG. 6 is a timing diagram of an example aligned address read access according to an embodiment of the invention. FIG. 7 is a timing diagram of an example unaligned address read access according to an embodiment of the invention. Fig. 8 is a timing diagram of an example DWA read access according to an embodiment of the invention. Fig. 9 is a timing diagram of another example DWA read access according to an embodiment of the invention. FIG. 10 is a timing diagram of an example DWA read access for word access according to an embodiment of the present invention. FIG. 11 is a timing diagram of an example DWA read access for byte access according to an embodiment of the present invention. Fig. 12 is a timing diagram of an example modified DWA read access for word access according to an embodiment of the invention. Fig. 13 is a timing diagram of an example modified DWA read access for byte access according to an embodiment of the invention. Fig. 14 is a timing diagram of an example modified DWA read access for double word access according to an embodiment of the invention. FIG. 15 is a flowchart of an example method of controlling a read request according to an embodiment of the invention. Detailed Description Reference will now be made in detail to the specific embodiments of the present invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to