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CN-115917972-B - Complementary 2 (N) bit redundancy for single event upset prevention

CN115917972BCN 115917972 BCN115917972 BCN 115917972BCN-115917972-B

Abstract

The present disclosure describes various aspects of complementary 2 (N) bit redundancy for Single Event Upset (SEU) prevention. In some aspects, an integrated circuit (104) includes a data storage element (206) for storing a data value, another data storage element (202) for storing a complementary data value, a multi-bit data storage element (e.g., 2-bit storage element (204)) for storing both the data value and the complementary data value, and voting logic (124) that can enable a complementary data storage scheme with inter-circuit redundancy for preventing SEU. Additionally, the voting logic of the integrated circuit may enable detection and correction of data value errors and/or programming of voting logic criteria, which may be dynamically implemented based on the type of SEU fault detected or corrected.

Inventors

  • Sayid Shakir Iqbal

Assignees

  • 谷歌有限责任公司

Dates

Publication Date
20260512
Application Date
20210621

Claims (15)

  1. 1. An integrated circuit, comprising: -an input node (226), the input node (226) for receiving a data value; A first data storage element (206), the first data storage element (206) having an input operably coupled to the input node, the first data storage element configured to store the data value; at least one inverter (230), the at least one inverter (230) being operably coupled to the input node to provide a complementary data value; A second data storage element (202), the second data storage element (202) having an input operably coupled to the at least one inverter, the second data storage element configured to store the complementary data value; a multi-bit data storage element (204), the multi-bit data storage element (204) having a first input operably coupled to the input node and a second input operably coupled to the at least one inverter, the multi-bit data storage element configured to store the data value and the complementary data value as separate values, and Voting logic (124), the voting logic (124) comprising: An output coupled to an output node (228) of the integrated circuit; A first input of the voting logic operably coupled to an output of the first data storage element (206) to receive a first logic value based on the data value stored by the first data storage element; A second input of the voting logic operably coupled to an output of the second data storage element (202) to receive a second logic value based on the complementary data value stored by the second data storage element; A third input of the voting logic coupled to a first output of the multi-bit data storage element (204) to receive a third logic value based on the data value stored by the multi-bit data storage element, and A fourth input of the voting logic, the fourth input of the voting logic coupled to a second output of the multi-bit data storage element (204) to receive a fourth logic value based on the complementary data value stored by the multi-bit data storage element, The voting logic is configured to provide an output data value to the output node of the integrated circuit based on a first set of logic values that includes at least three of the first logic value, the second logic value, the third logic value, and the fourth logic value.
  2. 2. The integrated circuit of claim 1, wherein the at least one inverter operably coupled to the input node comprises: a first inverter operably coupled between the input node and the input of the second data storage element, and A second inverter operably coupled between the input node and the second input of the multi-bit data storage element.
  3. 3. The integrated circuit of claim 1, wherein the at least one inverter operably coupled to the input node comprises a first inverter, and the integrated circuit further comprises at least one of: A second inverter operably coupled between the output of the second data storage element and the second input of the voting logic, and A third inverter operably coupled between the second output of the multi-bit data storage element and the fourth input of the voting logic.
  4. 4. The integrated circuit of claim 3, wherein at least one of the first inverter, the second inverter, and the third inverter comprises an inverting logic gate implemented external to the first data storage element, the second data storage element, and the multi-bit data storage element.
  5. 5. The integrated circuit of claim 1, wherein the multi-bit data storage element further comprises: a first latch circuit configured to store the data value; a second latch circuit configured to store the complementary data value, and Shared clock logic operably coupled to the first latch circuit and the second latch circuit.
  6. 6. The integrated circuit of claim 5, wherein: the first latch circuit includes at least one of a first flip-flop and a first 1-bit storage element of the multi-bit data storage element; the second latch circuit includes at least one of a second flip-flop and a second 1-bit storage element of the multi-bit data storage element.
  7. 7. The integrated circuit of claim 1, wherein: The voting logic is configured to provide the output data value using a majority voting function based on: -said first logical value based on said data value stored by said first data storage element; and (c) a second logic value based on the complementary data value stored by the second data storage element, and Or based on the third logical value of the data value stored by the multi-bit data storage element The voting logic is configured to provide the output data value using a majority voting function based on: -said first logical value based on said data value stored by said first data storage element; and (c) a second logic value based on the complementary data value stored by the second data storage element, and The fourth logic value based on the complementary data value stored by the multi-bit data storage element.
  8. 8. The integrated circuit of claim 1, wherein: The voting logic is configured to provide the output data value using a majority voting function based on: -said first logical value based on said data value stored by said first data storage element; And (c) a second logic value based on a non-inverted version of the complementary data value stored by the second data storage element, and The third logical value based on the data value stored by the multi-bit data storage element.
  9. 9. The integrated circuit of claim 1, wherein: the voting logic is further configured to: detecting a single event upset SEU based on the first set of logical values, and In response to detecting the SEU, changing configurable logic of the voting logic to provide the output data value using a second set of logic values, the second set of logic values including at least three of the first logic value, the second logic value, the third logic value, and the fourth logic value, the first set of logic values being different from the second set of logic values.
  10. 10. The integrated circuit of claim 9, wherein: The voting logic further comprises respective exclusive-or circuits of complementary pairs of the first logic value, the second logic value, the third logic value, and the fourth logic value, the exclusive-or circuits configured to detect the SEU.
  11. 11. The integrated circuit of claim 10, wherein: The voting logic is further configured to change the configurable logic of the voting logic to implement a triple module redundant TMR mode in response to detecting the SEU, in which the voting logic implements a voting function based on: -said first logical value based on said data value stored by said first data storage element; And (c) a second logic value based on a non-inverted version of the complementary data value stored by the second data storage element, and The third logical value based on the data value stored by the multi-bit data storage element.
  12. 12. The integrated circuit of any of claims 1 to 11, wherein the first data storage element, the second data storage element, or the multi-bit data storage element are implemented as one or more of: Latches, bi-stable latches, set-reset latches (SR latches), master-slave latches, D latches, flip-flops, D flip-flops, T flip-flops, JK flip-flops, master-slave flip-flops, 1-bit registers, multi-bit registers, logic memory cells, charge storage cells, and clock data storage circuits.
  13. 13. A method performed by an integrated circuit, the method comprising: receiving a data value at an input of a complementary multi-bit redundancy circuit; storing the data value to a first 1-bit data storage element of the complementary multi-bit redundancy circuit; Generating, via data inversion circuitry, a complementary data value based on the data value, the complementary data value having a logic state opposite to a logic state of the data value; Storing the complementary data value from the data inversion circuitry to a second 1-bit data storage element of the complementary multi-bit redundancy circuit; storing the data value to a first storage element of a multi-bit data storage element of the complementary multi-bit redundancy circuit; A second storage element storing the complementary data value from the data inversion circuitry to the multi-bit data storage element of the complementary multi-bit redundancy circuit, and An output data value is generated based on at least three of the data value stored by the first 1-bit data storage element, the complementary data value stored by the second 1-bit data storage element, the data value stored to the first storage element of the multi-bit data storage element, and the complementary data value stored to the second storage element of the multi-bit data storage element using voting logic of the complementary multi-bit redundancy circuit.
  14. 14. The method of claim 13, the method further comprising: Monitoring a pair of complementary data values comprising one of the data values stored by the first 1-bit data storage element or the first storage element of the multi-bit data storage element and one of the complementary data values stored by the second 1-bit data storage element and the second storage element of the multi-bit data storage element; Detecting a failure of one of the first 1-bit data storage element, the second 1-bit data storage element, the first storage element of the multi-bit data storage element, or the second storage element of the multi-bit data storage element based on the pair of complementary data values, and The voting logic is changed to troubleshoot storage elements of either the 1-bit data storage element or the multi-bit data storage element.
  15. 15. The method of claim 14, wherein a respective data value or complementary data value of one of the first 1-bit data storage element, the second 1-bit data storage element, the first storage element of the multi-bit data storage element, or the second storage element of the multi-bit data storage element is not used by the voting logic to provide the output data value, and further comprising: The voting logic is changed to include the respective data value or complementary data value of the first 1-bit data storage element, the second 1-bit data storage element, the first storage element of the multi-bit data storage element, or the second storage element of the multi-bit data storage element that was not previously used by the voting logic to provide the output data value.

Description

Complementary 2 (N) bit redundancy for single event upset prevention Background Without protection, integrated circuits are often vulnerable to certain environmental conditions, such as when exposed to solar radiation. For example, charged solar particles may strike a node of an integrated circuit, resulting in a sudden spike in voltage. This phenomenon is known as Single Event Transient (SET). When a SET occurs at or propagates to a register input during a SET up/hold window of a latch circuit, there is a risk that the SET is captured by circuitry. When a SET is captured by a latch circuit, the SET causes a Single Event Upset (SEU) that may affect the output value of the latch circuit. Thus, SEU may cause significant failure by causing errors in the nodes of the logic element by changing the bit value from an expected "1" value to an incorrect "0" value or from an expected "0" value to an incorrect "1" value. These circuit level errors may adversely affect the operation of many types of safety or mission critical devices including aircraft, voting machines, medical devices, satellites, and the like. Therefore, it is important to minimize SEU vulnerabilities of the circuit and related problems that may affect the operation of various types of electronic devices. Previous SEU prevention techniques have attempted to reduce the likelihood of SEU by creating hardware redundancy within the integrated circuit. These redundant elements are separated by a technology-specific distance to offset the risk of naturally occurring SEU affecting all redundant elements. For example, triple Module Redundancy (TMR) replicates each critical latch/flip-flop, requiring three compliance SEU tolerances. However, these redundancies do not address the inherent vulnerability of intentional attacks. Such an attack can be easily performed when an attacker knows the approximate distance between redundant circuit elements, and since the redundant elements are identical, an attack that is valid for one element will be valid for the other element. Thus, previous SEU prevention techniques may not be sufficient to defend against malicious actors or otherwise occurring SETs. Disclosure of Invention The present disclosure describes devices and techniques for preventing complementary 2 (N) bit redundancy for Single Event Upset (SEU). In some aspects, an integrated circuit includes a data storage element for storing a data value, another data storage element for storing a complementary data value, a multi-bit data storage element (e.g., a 2-bit storage element) for storing both the data value and the complementary data value, and voting logic that can enable a complementary data storage scheme with inter-circuit redundancy for SEU prevention. Additionally, the voting logic of the integrated circuit may enable detection and correction of data value errors and/or programming of voting logic criteria, which may be dynamically implemented based on the type of SEU fault detected or corrected. In one aspect, a complementary 2 (N) bit redundancy integrated circuit for SEU prevention includes an input node for receiving a data value, and a first data storage element having an input operatively coupled to the input node, the first data storage element configured to store the data value. The integrated circuit further includes at least one inverter operatively coupled to the input node to provide a complementary data value, and a second data storage element having an input operatively coupled to the at least one inverter, the second data storage element configured to store the complementary data value. The multi-bit data storage element of the integrated circuit has a first input operatively coupled to the input node and a second input operatively coupled to the at least one inverter. The multi-bit data storage element is configured to store a data value and a complementary data value as separate values. The integrated circuit includes a voter logic having an output coupled to an output node of the integrated circuit, and a first input operatively coupled to an output of the first data storage element to receive a first logic value based on a data value stored by the first data storage element. The voting logic also includes a second input operatively coupled to the output of the second data storage element to receive a second logic value based on the complementary data value stored by the second data storage element, a third input coupled to the first output of the multi-bit data storage element to receive a third logic value based on the data value stored by the multi-bit data storage element, and a fourth input coupled to the second output of the multi-bit data storage element to receive a fourth logic value based on the complementary data value stored by the multi-bit data storage element. In aspects, the voter logic is configured to provide the output data value to an output node of the integrated circuit based on respective sets of logic values of