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CN-115933808-B - Multichannel DDS signal source

CN115933808BCN 115933808 BCN115933808 BCN 115933808BCN-115933808-B

Abstract

The invention discloses a multi-channel DDS signal source which comprises an FPGA, a clock chip, a clock fan-out chip and a plurality of DDS signal channels, wherein the DDS signal channels comprise a DDS chip, a balun, a low-pass filter, a variable attenuator, a fixed attenuator, an amplifier and an analog switch which are sequentially connected, the clock chip respectively provides a sampling clock for each DDS chip and a reference clock for the FPGA, the clock fan-out chip respectively provides a SYNC_IN signal for each DDS chip, the FPGA is used for monitoring the SYNC_SMP_ERR signal of each DDS chip, if the SYNC_SMP_ERR signal is monitored to be high level, the delay value of each DDS chip for receiving the SYNC_IN signal is dynamically adjusted, and the attenuation value of each variable attenuator is respectively controlled according to a preset passband inner amplitude curve.

Inventors

  • BAI YAOHUA
  • Lin haichuan
  • JIANG WANSHU
  • XU CHAO
  • YU YUHONG
  • GAO JIALE

Assignees

  • 成都中微达信科技有限公司

Dates

Publication Date
20260505
Application Date
20221229

Claims (8)

  1. 1. A multi-channel DDS signal source is characterized by comprising an FPGA, a clock chip, a clock fan-out chip and a plurality of DDS signal channels, wherein, The DDS signal channel comprises a DDS chip, a balun, a low-pass filter, a variable attenuator, a fixed attenuator, an amplifier and an analog switch which are connected in sequence; The clock chip is used for providing a sampling clock for the DDS chip of each DDS signal channel and providing a reference clock for the FPGA; The clock fan-out chip is used for providing SYNC_IN signals for the DDS chips of each DDS signal channel respectively; The FPGA is respectively connected with the DDS chip, the variable attenuator and the analog switch of each DDS signal channel and is used for monitoring the SYNC_SMP_ERR signal of each DDS chip, dynamically adjusting the delay value of each DDS chip for receiving the SYNC_IN signal if the SYNC_SMP_ERR signal is monitored to be IN a high level; The length of the wires from the clock chip to the sampling clock input pins of the DDS chips of each DDS signal channel is equal, and the length of the wires from the clock fan-out chip to the SYNC_IN signal input pins of the DDS chips of each DDS signal channel is equal; The FPGA is respectively connected to the I/O_RESET pins of the DDS chips of each DDS signal channel, the FPGA is respectively connected to the SYNC_CLK pins of the DDS chips of each DDS signal channel, the FPGA is respectively connected to the I/O_UPDATE pins of the DDS chips of each DDS signal channel, and the FPGA is respectively connected to the PROFILE pins of the DDS chips of each DDS signal channel.
  2. 2. A multi-channel DDS signal source as recited in claim 1, wherein the FPGA is configured to output the I/O_RESET signal, the I/O_UPDATE signal, and the PROFILE signal via the programmable input-output unit, and to output the I/O_UPDATE signal to the I/O_UPDATE pin of the DDS chip and/or the PROFILE signal to the PROFILE pin of the DDS chip upon a falling edge of the SYNC_CLK signal.
  3. 3. The multi-channel DDS signal source of claim 1 wherein the signal input of said clock fan-OUT chip is provided by a signal output from the sync_out pin of one of said DDS chips.
  4. 4. A multi-channel DDS signal source as recited in claim 1 wherein said variable attenuator provides an attenuation step of 0.5 dB.
  5. 5. A multi-channel DDS signal source as claimed in any one of claims 1 to 4 wherein said FPGA is configured to control the operation of said clock chip and each DDS chip in accordance with its loaded program.
  6. 6. The multi-channel DDS signal source according to claim 5, wherein the FPGA is connected with a FLASH module and a DDR3 module, wherein, The FLASH module is used for storing the program of the FPGA; And the DDR3 module is used for caching the operation data of the FPGA.
  7. 7. The multi-channel DDS signal source according to claim 6, further comprising a digital power module and an analog power module, wherein, The digital power module is used for providing power for the FPGA, the FLASH module and the DDR3 module; The analog power supply module is used for providing power for the clock chip, the DDS chip, the variable attenuator, the amplifier and the analog switch in each DDS signal channel.
  8. 8. The multi-channel DDS signal source of claim 1 wherein said FPGA is configured with a network interface or serial interface for interacting with a host computer.

Description

Multichannel DDS signal source Technical Field The invention relates to the technical field of digital signal processing, in particular to a multi-channel DDS signal source. Background The Direct Digital Synthesizer (DDS) has the advantages of digitally controlled and adjustable output signal frequency, phase and amplitude, high output frequency resolution, quick frequency change and the like, and can be widely applied to the fields of communication, radar, ultrasonic waves and the like. And as the bandwidth of the intermediate frequency signal output by the DDS is required to be higher and higher, a great challenge is brought to the synchronous precision of the DDS and the control design of the flatness in the passband. Disclosure of Invention The embodiment of the invention provides a multi-channel DDS signal source, which not only can improve the synchronization precision of signal channels, but also can realize the step attenuation function of amplitude under the condition of ensuring the output flatness. In order to achieve the above object, the present invention provides the following technical solutions: A multi-channel DDS signal source comprises an FPGA, a clock chip, a clock fan-out chip and a plurality of DDS signal channels, wherein, The DDS signal channel comprises a DDS chip, a balun, a low-pass filter, a variable attenuator, a fixed attenuator, an amplifier and an analog switch which are connected in sequence; The clock chip is used for providing a sampling clock for the DDS chip of each DDS signal channel and providing a reference clock for the FPGA; The clock fan-out chip is used for providing SYNC_IN signals for the DDS chips of each DDS signal channel respectively; The FPGA is respectively connected with the DDS chip, the controllable decay device and the analog switch of each DDS signal channel and is used for monitoring the SYNC_SMP_ERR signal of each DDS chip, dynamically adjusting the delay value of each DDS chip for receiving the SYNC_IN signal if the SYNC_SMP_ERR signal is monitored to be IN a high level, respectively controlling the attenuation value of each variable attenuator according to the amplitude curve IN a preset passband, and respectively controlling the corresponding analog switches to conduct the corresponding DDS signal channels according to the set channel number. IN a specific embodiment, the lengths of the wires from the clock chip to the sampling clock input pins of the DDS chips of each DDS signal channel are equal, and the lengths of the wires from the clock fan-out chip to the sync_in signal input pins of the DDS chips of each DDS signal channel are equal. In a specific embodiment, the lengths of the wires of the I/o_reset pins of the DDS chips connected to each DDS signal channel are equal, the lengths of the wires of the sync_clk pins of the DDS chips connected to each DDS signal channel are equal, the lengths of the wires of the I/o_update pins of the DDS chips connected to each DDS signal channel are equal, and the lengths of the wires of the PROFILE pins of the DDS chips connected to each DDS signal channel are equal. In a specific embodiment, the FPGA is configured to output the I/O_RESET signal, the I/O_UPDATE signal and the PROFILE signal through the programmable input-output unit, and, upon a falling edge of the SYNC_CLK signal, output the I/O_UPDATE signal to the I/O_UPDATE pin of the DDS chip and/or output the PROFILE signal to the PROFILE pin of the DDS chip. In a specific embodiment, the signal input of the clock fan-OUT chip is provided by a signal output from the sync_out pin of one of the DDS chips. In a specific embodiment, the variable attenuator provides an attenuation step of 0.5 dB. In a specific embodiment, the FPGA is configured to control the operation of the clock chip and each DDS chip according to the program it loads. In a specific implementation mode, the FPGA is connected with a FLASH module and a DDR3 module, wherein the FLASH module is used for storing programs of the FPGA, and the DDR3 module is used for caching operation data of the FPGA. In a specific embodiment, the multi-channel DDS signal source further comprises a digital power module and an analog power module, wherein the digital power module is used for providing power for the FPGA, the FLASH module and the DDR3 module, and the analog power module is used for providing power for the clock chip, the DDS chip, the variable attenuator, the amplifier and the analog switch in each DDS signal channel. In a specific embodiment, the FPGA is configured with a network interface or a serial interface for interacting with a host computer. Therefore, the embodiment of the invention provides the multi-channel DDS signal source, which not only can improve the synchronous precision of the signal channels, but also can realize the step attenuation function of amplitude under the condition of ensuring the output flatness. Description of the drawings: fig. 1 is a schematic diagram of a arc