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CN-115935897-B - PCBA carrier plate model generation method, system, electronic equipment and storage medium

CN115935897BCN 115935897 BCN115935897 BCN 115935897BCN-115935897-B

Abstract

The invention relates to a PCBA carrier plate model generation method, a system, electronic equipment and a storage medium, wherein the method comprises the steps of obtaining basic data; the method comprises the steps of obtaining a final avoidance contour line of a to-be-detected jointed board based on the avoidance contour lines of all components and PCBA outer contour lines of the to-be-detected jointed board, obtaining the avoidance depth of the to-be-detected jointed board based on the avoidance depth of the components and the preset minimum avoidance depth of the to-be-detected jointed board, generating corresponding avoidance grooves on a carrier board based on the final avoidance contour line of the to-be-detected jointed board, the avoidance depth of the to-be-detected jointed board and the layout data of the to-be-detected jointed board, obtaining a second support area based on the final avoidance contour line of the to-be-detected jointed board, generating a first board support based on the second support area and the avoidance depth of the to-be-detected jointed board, and generating radio frequency through holes, hand taking positions and surrounding block grooves on the carrier board to generate a final carrier board model. The method improves the working efficiency and the accuracy of generating the carrier plate model, and saves the design cost for enterprises.

Inventors

  • WEI TAO
  • LIU JISHUO
  • LIU FENGSHOU

Assignees

  • 上海望友信息科技有限公司

Dates

Publication Date
20260505
Application Date
20221205

Claims (17)

  1. 1. The PCBA carrier plate model generation method is characterized by comprising the following steps of: the method comprises the steps of obtaining basic data, wherein the basic data comprises a carrier board template file and to-be-detected jointed board data, the carrier board template file comprises to-be-detected jointed board layout data, the to-be-detected jointed board layout data comprises the number, coordinates and angles of to-be-detected jointed boards, and the to-be-detected jointed board data comprises PCBA outline lines, PCBA layout data, component data on PCBA and safety intervals between a carrier board and components; Obtaining the avoidance contour lines of all components on the to-be-detected jointed board based on the component data on the PCBA, and obtaining the final avoidance contour line of the to-be-detected jointed board based on the avoidance contour lines of all components on the to-be-detected jointed board and the PCBA outer contour line; obtaining the avoidance depth of the component based on the component data on the PCBA and the safety distance between the carrier plate and the component, obtaining the avoidance depth of the to-be-detected jointed board based on the avoidance depth of the component and the preset minimum avoidance depth of the to-be-detected jointed board, and generating a corresponding avoidance groove on the carrier plate based on the final avoidance contour line of the to-be-detected jointed board, the avoidance depth of the to-be-detected jointed board and the layout data of the to-be-detected jointed board; Obtaining a first support area based on the final avoidance contour line of the to-be-detected jointed board and the to-be-detected jointed board data, obtaining a second support area based on the first support area and the to-be-detected jointed board layout data, taking the bottom of the avoidance groove of the carrier plate as a starting surface, stretching the second support area to be the avoidance depth of the to-be-detected jointed board, and stretching the second support area to generate a first board surface support on the carrier plate, wherein the number M of to-be-detected jointed boards is obtained according to the to-be-detected jointed board layout data, if M >1, the first support area is subjected to coordinate and angle transformation according to the to-be-detected jointed board layout data to obtain the second support area, if M=1, the first support area is the second support area, the first support area is all support areas to be detected singly, and the second support area is all support areas corresponding to all to-be-detected jointed boards; and generating a radio frequency through hole, a hand taking position and a surrounding block groove on the carrier plate so as to generate a final carrier plate model.
  2. 2. The carrier pattern generation method of claim 1, wherein the component data on the PCBA includes an outer contour of a component; the step of obtaining the avoidance contour lines of all components on the to-be-detected jointed board based on the component data on the PCBA, and obtaining the final avoidance contour lines of the to-be-detected jointed board based on the avoidance contour lines of all components on the to-be-detected jointed board and the PCBA outer contour lines comprises the following steps: expanding the outer contour line of each component on the jointed board to be tested outwards by a first preset value to obtain the avoidance contour lines of all components on the jointed board to be tested; merging the area surrounded by the avoidance contour lines of all components on the jointed board to be tested with the area surrounded by the PCBA outer contour lines, and taking the outer contour line of the merged area as the initial avoidance contour line of the jointed board to be tested; And carrying out regular treatment on the initial avoidance contour line of the to-be-detected jointed board according to the concavity and convexity of the initial avoidance contour line of the to-be-detected jointed board to obtain the final avoidance contour line of the to-be-detected jointed board, wherein each line segment in the final avoidance contour line of the to-be-detected jointed board is a horizontal or vertical line segment, and carrying out rounding treatment on the final avoidance contour line of the to-be-detected jointed board.
  3. 3. The carrier pattern generation method of claim 1, wherein the component data on the PCBA further includes a height of the component after installation, and the safety pitch of the carrier and the component includes a lateral avoidance pitch and a depth avoidance pitch of the component; The step of obtaining the avoidance depth of the component based on the component data on the PCBA and the safety distance between the carrier plate and the component, and obtaining the avoidance depth of the to-be-tested jointed board based on the avoidance depth of the component and the minimum avoidance depth preset by the to-be-tested jointed board comprises the following steps: Adding the depth clearance space corresponding to each component on the to-be-detected jointed board to the installed height of each component to obtain the clearance depth of each component; and taking the larger value of the maximum value of the avoidance depths in all the components and the minimum avoidance depth preset by the jointed board to be tested as the avoidance depth of the jointed board to be tested.
  4. 4. The carrier pattern generation method of claim 1, wherein the panel data to be tested further comprises PCBA inner contours; the step of obtaining a first supporting area based on the final avoidance contour line of the to-be-detected jointed board and the to-be-detected jointed board data comprises the following steps: removing the area surrounded by the avoidance contour lines of all the components in the area surrounded by the final avoidance contour line of the to-be-detected jointed board, and removing the area surrounded by the internal contour line of the PCBA to obtain an initial supportable area of the to-be-detected jointed board according to the remaining area; removing the area smaller than the second preset value and/or the area with the set distance smaller than the third preset value in the initial supportable area of the to-be-detected jointed board to obtain the to-be-supported area of the to-be-detected jointed board; And carrying out regular treatment on the outer contour line of the to-be-supported area of the to-be-supported jointed board according to the concave-convex property of the outer contour line of the to-be-supported area of the to-be-supported jointed board to obtain the first supporting area, wherein each line segment in the outer contour line of the first supporting area is a horizontal or vertical line segment, and carrying out rounding treatment on the outer contour line of the first supporting area.
  5. 5. The carrier board model generation method of claim 1, wherein the base data further comprises a three-dimensional CAD file of a shield, the model generation method further comprising: acquiring the height of a shielding cover supporting contour line and a shielding cover supporting area based on the three-dimensional CAD file of the shielding cover; And obtaining a shielding cover supporting area based on the shielding cover supporting contour line, determining a first shielding cover supporting area based on the shielding cover supporting area, obtaining a second shielding cover supporting area based on the first shielding cover supporting area, taking the bottom of the avoidance groove of the carrier plate as a starting surface, stretching the second shielding cover area to be the height of the shielding cover supporting area, carrying out additive stretching on the second shielding cover area, and generating a second plate surface support on the carrier plate, wherein the first shielding cover supporting area is all shielding cover supporting areas of a single jointed board to be tested, and the second shielding cover supporting area is all shielding cover supporting areas corresponding to all jointed boards to be tested.
  6. 6. The carrier board model generation method of claim 5, wherein the three-dimensional CAD file of the shield includes a three-dimensional model of the shield; The method comprises the steps of obtaining a shielding cover supporting contour line and the height of a shielding cover supporting area based on a three-dimensional CAD file of the shielding cover, obtaining the shielding cover supporting area based on the shielding cover supporting contour line, determining a first shielding cover supporting area based on the shielding cover supporting area, and obtaining a second shielding cover supporting area based on the first shielding cover supporting area, wherein the steps comprise: Acquiring the surface of the top of the shielding case according to the three-dimensional model of the shielding case, and obtaining the height value H1 from the top surface to the mounting surface of each shielding case; projecting the top surface of the shielding case to a mounting surface to obtain a supporting contour line of the shielding case; inwardly shrinking the supporting contour line of the shielding cover by a fourth preset value to obtain the inner contour line of the supporting area corresponding to the top surface of the shielding cover; Obtaining an initial supporting area of the shielding cover according to an annular area surrounded by the supporting contour line of the shielding cover and the inner contour line of the supporting area of the shielding cover, wherein the height of the initial supporting area of the shielding cover is obtained by subtracting a corresponding height value H1 from the depth of the avoidance groove; the method comprises the steps of obtaining a shielding cover supporting area by filling and removing an area, in which the gap in the inner contour line of the shielding cover initial supporting area is smaller than a fifth preset value, of the shielding cover initial supporting area, wherein the height of the shielding cover supporting area is the height of the corresponding shielding cover initial supporting area; and determining the first shielding cover supporting area based on the to-be-detected jointed board data and the shielding cover supporting area, and obtaining the second shielding cover supporting area based on the first shielding cover supporting area.
  7. 7. The carrier pattern generation method of claim 6, wherein the step of determining the first shield support area based on the panel data to be tested and the shield support area, and obtaining the second shield support area based on the first shield support area, comprises: Based on the to-be-tested jointed board data, carrying out coordinate, angle and mirror image transformation on the same PCBA data in a single to-be-tested jointed board according to the PCBA layout data to obtain a third shielding cover supporting area, obtaining the number N of PCBA types of different PCBA data in the single to-be-tested jointed board, wherein the summary of the shielding cover supporting areas corresponding to the N PCBA data is the third shielding cover supporting area, and summarizing the third shielding cover supporting area corresponding to the same PCBA data and the third shielding cover supporting area corresponding to different PCBA data to obtain a first shielding cover supporting area, wherein the shielding cover supporting area is the shielding cover supporting area corresponding to the single PCBA data, and the third shielding cover supporting area is the shielding cover supporting area corresponding to a plurality of PCBA data; and acquiring the number M of the to-be-detected jointed boards according to the to-be-detected jointed board layout data, and carrying out coordinate and angle transformation on the first shielding cover supporting area according to the to-be-detected jointed board layout data to obtain the second shielding cover supporting area if M is more than 1, wherein the first shielding cover supporting area is the second shielding cover supporting area if M is less than 1.
  8. 8. The carrier plate model generating method according to claim 7, wherein the generating method further comprises, after generating the second plate surface support on the carrier plate, taking the bottom of the avoidance groove of the carrier plate as a starting surface, stretching the second shield cover region to be additive-stretched to a height equal to that of the shield cover support region: Judging the relation between the minimum distance between every two shield cover supporting areas in the first shield cover supporting areas and the fifth preset value, and if the minimum distance is smaller than the fifth preset value, obtaining a first gap area based on the corresponding two shield cover supporting areas through a gap area calculation method, wherein the height to be stretched of the first gap area is a smaller value of the heights corresponding to the corresponding two shield cover supporting areas; Judging the relation between the shielding case supporting area in the first shielding case supporting area or the minimum distance between the first clearance area and the first supporting area and the fifth preset value, if the minimum distance is smaller than the fifth preset value, obtaining a second clearance area through a clearance area calculation method based on the corresponding shielding case supporting area or the corresponding first clearance area and the corresponding first supporting area, wherein the height to be stretched of the second clearance area is a smaller value of the heights of the two corresponding areas; Obtaining a third gap area according to the first gap area and the second gap area, obtaining a fourth gap area according to the third gap area and the layout data of the to-be-tested jointed boards, taking the bottom of the avoidance groove of the carrier plate as a starting surface, stretching the fourth gap area to be the corresponding to the first gap area or the to-be-stretched height of the second gap area, and stretching the fourth gap area to complete filling of all the gap areas, wherein the number M of the to-be-tested jointed boards is obtained according to the layout data of the to-be-tested jointed boards, if M is greater than 1, the third gap area is subjected to coordinate and angle transformation according to the layout data of the to-be-tested jointed boards, and obtaining the fourth gap area, if M=1, the third gap area is the fourth gap area, the third gap area is all the gap areas of a single to-be-tested jointed board, and the fourth gap area is all the gap areas corresponding to all the to-be-tested jointed boards.
  9. 9. The carrier pattern generation method according to claim 8, wherein the gap region calculation method includes: Expanding the first area and the second area outwards by W1/Q to obtain a third area and a fourth area, wherein W1 is the fifth preset value, Q is more than or equal to 1 and less than or equal to 2, and the first area and the second area are gap areas to be filled; Combining the third region and the fourth region through Boolean operation to obtain an outer contour line of the combined region; The method comprises the steps of carrying out normalization processing on outer contour lines of a merging area according to the concave-convex properties of the outer contour lines of the merging area to obtain first contour normalization lines, wherein each line segment in the first contour normalization lines is a horizontal or vertical line segment; Inwardly shrinking the first contour regular line by W1/Q, and chamfering the inwardly shrunk first contour regular line to obtain a second contour regular line; and removing the first area and the second area in the area surrounded by the second contour regular line through Boolean operation so as to obtain the gap area according to the rest area.
  10. 10. The carrier plate model generation method of claim 5, further comprising: Determining a final reinforcing region based on a parallel relationship between two straight line segments of each supporting region in the first supporting region, so as to generate a reinforcing rib according to the final reinforcing region, wherein the method comprises the following steps of: Traversing all straight line segments of each support area in the first support area, and for any one straight line segment, if a rounding angle exists at the end point of the straight line segment, extending the straight line segment from the end point along the straight line segment by a preset length, wherein the preset length is the radius of the corresponding rounding angle; after the extension treatment is carried out on all the straight line segments with the fillets, judging whether two parallel straight line segments exist, the distance between the two parallel straight line segments is smaller than a sixth preset value, the two parallel straight line segments are projected to be overlapped in the vertical direction, and an intersection exists between an area surrounded by the overlapped part and the first supporting area, if yes, an area needing to be reinforced is obtained according to the area surrounded by the overlapped part; Extending the region to be reinforced along the extending direction by a seventh preset value to obtain a reinforced region, wherein the extending direction is a projection direction, and the height of the reinforced region is equal to the depth of the avoidance groove minus the maximum value of the avoidance depths of all the components in the reinforced region; For each region to be reinforced, selecting one from all the reinforced regions corresponding to the region to be reinforced as a reinforced region corresponding to the region to be reinforced according to a preset rule, and summarizing all reinforced regions corresponding to all the regions to be reinforced to obtain the final reinforced region; and obtaining a first reinforcing area according to the final reinforcing area and the layout data of the to-be-detected jointed boards, wherein the bottom of the avoidance groove of the carrier plate is used as an initial surface, the stretching height is the height corresponding to the reinforced area, the first reinforcing area is subjected to additive stretching, the reinforcing ribs are generated on the carrier plate, the number M of the to-be-detected jointed boards is obtained according to the layout data of the to-be-detected jointed boards, if M is more than 1, the final reinforcing area is subjected to coordinate and angle transformation according to the layout data of the to-be-detected jointed boards, the first reinforcing area is obtained, if M=1, the final reinforcing area is the first reinforcing area, the final reinforcing area is all reinforcing areas of a single to-be-detected jointed board, the first reinforcing area is all reinforcing areas corresponding to all to-be-detected jointed boards, and the corner of the reinforcing ribs is subjected to chamfering treatment.
  11. 11. The carrier board model generating method according to claim 10, wherein the preset rule includes A1, A2, A3, and A4 in order from high to low according to priority, wherein: a1 is that the smaller the area of the bounding box formed by the reinforced area and the area needing to be reinforced is, the higher the priority is; a2 is higher priority as the height of the reinforced area is larger; A3 is the higher priority the greater the distance of the reinforced area from the first support area and/or the second shield support area; a4 is the higher priority the larger the distance between the reinforced area and the final avoidance contour line of the jointed board to be tested.
  12. 12. The carrier pattern generation method according to claim 2, 4 or 9, wherein the method of normalization specifically comprises: S1, judging the shape of each line segment in a first contour line to be processed in a regular manner along a preset direction, and if the line segment is a horizontal or vertical straight line segment, not processing, if the line segment is an arc, continuing judging the outward convex and inward concave conditions of the arc, outwards regulating the convex arc, inwards regulating the concave arc, and if the line segment is other line segments except the horizontal or vertical straight line segment and the arc, outwards regulating or inwards regulating according to the set conditions, wherein when outwards regulating, the region surrounded by the bounding box of the line segment is combined with the region surrounded by the first contour line to be processed, and when inwards regulating, removing the region surrounded by the bounding box of the line segment from the region surrounded by the first contour line to be processed; S2, deleting a line segment with the length smaller than 2 times of the radius of the rounding angle in the first contour line to be processed, deleting two line segments adjacent to the line segment, connecting a notch formed by deleting the line segments by using straight line segments to form a closed second contour line to be processed, and iteratively executing the steps S1-S2 on the second contour line to be processed until the lengths of all the line segments are larger than or equal to a set value, so as to obtain a final regular contour line.
  13. 13. The carrier template generation method according to claim 5, wherein the carrier template file further comprises layout data of a pick-up position and layout data of a surrounding block groove, the to-be-detected jointed board data further comprises radio frequency through hole parameters on the PCBA and length and width of the to-be-detected jointed board, and the radio frequency through hole parameters comprise circle center coordinates and radius of all radio frequency through holes on the PCBA; the step of generating a radio frequency through hole, a hand taking position and a surrounding block groove on the carrier plate comprises the following steps: Obtaining a first radio frequency through hole based on radio frequency through hole parameters on the PCBA and the PCBA layout data, and obtaining a second radio frequency through hole according to the first radio frequency through hole and the to-be-tested jointed board layout data, wherein for the same PCBA data in a single to-be-tested jointed board, according to the PCBA layout data, carrying out coordinate, angle and mirror image transformation on radio frequency through holes corresponding to the same PCBA data, and obtaining a third radio frequency through hole; the method comprises the steps of obtaining the number N of different PCBA data in a single to-be-tested jointed board, obtaining the number M of the to-be-tested jointed boards according to the layout data of the to-be-tested jointed boards, and if M is greater than 1, carrying out coordinate and angle transformation on the first radio frequency through holes according to the layout data of the to-be-tested jointed boards to obtain second radio frequency through holes, and if M=1, obtaining the first radio frequency through holes to be the second radio frequency through holes, wherein the radio frequency through holes are all radio frequency through holes corresponding to the single PCBA, the first radio frequency through holes are all radio frequency through holes corresponding to the single to-be-tested jointed board, and the third radio frequency through holes are all radio frequency through holes corresponding to the plurality of PCBA data; Generating the hand taking position on the carrier plate based on the layout data of the hand taking position, the coordinates of the to-be-detected jointed boards in the layout data of the to-be-detected jointed boards, the length and the width of the to-be-detected jointed boards, and taking the top surface of the carrier plate as a starting surface, and rounding corners of the hand taking position, wherein the layout data of the hand taking position comprises overlapping size, number and groove depth; Based on the layout data of the surrounding block grooves, the coordinates of the to-be-detected jointed boards in the layout data of the to-be-detected jointed boards, and the length and the width of the to-be-detected jointed boards, the top surface of the carrier plate is used as a starting surface, the surrounding block grooves are formed on the carrier plate, corner corners of the surrounding block grooves are rounded, and the layout data of the surrounding block grooves comprise gap sizes, number and groove depths.
  14. 14. The carrier pattern generation method of claim 13, wherein the step of performing stability check on the second radio frequency through hole includes: For each radio frequency through hole in the second radio frequency through holes, taking the center of the radio frequency through hole as the center of a circle, taking R1 as the radius to make a circle, and obtaining a first supportable circular inspection area of the radio frequency through hole according to an area surrounded by the circle, wherein R1=R0+R, R0 is the radius of the radio frequency through hole, and R is an eighth preset value; Judging whether a preset fan-shaped area exists in a first supportable circular inspection area of the radio frequency through hole, if not, not removing, if so, removing the fan-shaped area, and taking the first supportable circular inspection area with the fan-shaped area removed as a second supportable circular inspection area, wherein the preset fan-shaped area comprises a first supporting area corresponding to PCBA data where the radio frequency through hole is located and/or a fan-shaped area occupied by a shielding cover supporting area in the first supportable circular inspection area, and a fan-shaped area occupied by an area outside a clearance groove of the carrier plate corresponding to PCBA data where the radio frequency through hole is located in the first supportable circular inspection area; Judging whether a continuous sector area with the sector angle larger than 180 degrees exists in the second supportable circular inspection area, if yes, marking the corresponding radio frequency through holes as unstable in support, otherwise, marking the corresponding radio frequency through holes as stable in support, and outputting an inspection report after all the radio frequency through holes are inspected.
  15. 15. A PCBA carrier plate model generation system, comprising: The system comprises an acquisition module, a display module and a display module, wherein the acquisition module is used for acquiring basic data, the basic data comprises a carrier template file and to-be-detected jointed board data, the carrier template file comprises to-be-detected jointed board layout data, the to-be-detected jointed board layout data comprises the number, coordinates and angles of to-be-detected jointed boards, and the to-be-detected jointed board data comprises PCBA outline lines, PCBA layout data, component data on the PCBA and the safety distance between a carrier board and a component; The avoidance contour line generation module is used for obtaining the avoidance contour lines of all components on the to-be-detected jointed board based on the component data on the PCBA, and obtaining the final avoidance contour line of the to-be-detected jointed board based on the avoidance contour lines of all components on the to-be-detected jointed board and the PCBA outer contour line; The avoidance groove generation module is used for obtaining the avoidance depth of the component based on the component data on the PCBA and the safety distance between the carrier plate and the component, obtaining the avoidance depth of the to-be-detected jointed board based on the avoidance depth of the component and the minimum avoidance depth preset by the to-be-detected jointed board, and generating a corresponding avoidance groove on the carrier plate based on the final avoidance contour line of the to-be-detected jointed board, the avoidance depth of the to-be-detected jointed board and the layout data of the to-be-detected jointed board; The first plate surface support generation module is used for obtaining a first support area based on the final avoidance contour line of the to-be-detected jointed plate and the to-be-detected jointed plate data, obtaining a second support area based on the first support area and the to-be-detected jointed plate layout data, taking the bottom of the avoidance groove of the carrier plate as a starting surface, stretching the second support area to be the avoidance depth of the to-be-detected jointed plate, and carrying out additive stretching on the carrier plate to generate a first plate surface support, wherein the number M of to-be-detected jointed plates is obtained according to the to-be-detected jointed plate layout data, if M is greater than 1, the first support area is subjected to coordinate and angle transformation according to the to-be-detected jointed plate layout data to obtain the second support area, and if M=1, the first support area is the second support area, and the first support area is all support areas of a single to-be-detected jointed plate and the second support area is all support areas corresponding to all to the to be-detected jointed plates; And the carrier plate model generation module is used for generating a radio frequency through hole, a hand taking position and a surrounding block groove on the carrier plate so as to generate a final carrier plate model.
  16. 16. The electronic equipment is characterized by comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory are communicated with each other through the communication bus; A memory for storing a computer program; a processor for implementing the method steps of any of claims 1-14 when executing said computer program.
  17. 17. A storage medium having stored therein a computer program which, when executed by a processor, implements the method steps of any of claims 1-14.

Description

PCBA carrier plate model generation method, system, electronic equipment and storage medium Technical Field The invention belongs to the technical field of electronic manufacturing, relates to a PCBA carrier plate model generation method, a system, electronic equipment and a storage medium, and in particular relates to a three-dimensional model automatic generation method, a system, electronic equipment and a storage medium of a carrier plate of a PCBA test fixture. Background The PCBA (Printed Circuit Board Assembly, printed circuit board) testing jig is very important equipment in PCBA processing factories, is special testing equipment, and is mainly used for testing various performances of PCBA on a PCBA production line. Among all the components of the PCBA test fixture, the carrier plate is an indispensable main component of the PCBA test fixture because of the main functions of positioning and supporting. Because the to-be-detected jointed boards are placed on the carrier plate in a back-off mode, enough avoiding space needs to be reserved when the carrier plate is designed so as not to damage precise components on the to-be-detected jointed boards. However, because the number of components on the jointed board to be tested is large and the types of the components are also large, the existing manual avoidance mode can be used for solving the problems of time and labor waste and easy error. In addition, when designing the carrier plate, also provide sufficient support for the makeup that awaits measuring to guarantee that the radio frequency probe can not make PCBA board take place too big deformation in test process, thereby lead to partial test point to deviate from original position and can't guarantee to be tested the needle normal test, appear damaging the phenomenon of PCBA board even, all need manual design about the design of supporting on the carrier plate, its requirement to the designer is also higher, consequently the design about supporting on the carrier plate also is the focus and the difficult point when the carrier plate design. Therefore, how to provide a method for generating a PCBA carrier model is a technical problem to be solved in the art, aiming at the design requirement of the carrier and the above mentioned shortcomings of the prior art. Disclosure of Invention In order to solve the problems in the prior art, the invention provides a PCBA carrier plate model generation method, a PCBA carrier plate model generation system, electronic equipment and a storage medium. The technical problems to be solved by the invention are realized by the following technical scheme: the invention provides a PCBA carrier plate model generation method, which comprises the following steps: the method comprises the steps of obtaining basic data, wherein the basic data comprises a carrier board template file and to-be-detected jointed board data, the carrier board template file comprises to-be-detected jointed board layout data, the to-be-detected jointed board layout data comprises the number, coordinates and angles of to-be-detected jointed boards, and the to-be-detected jointed board data comprises PCBA outline lines, PCBA layout data, component data on PCBA and safety intervals between a carrier board and components; Obtaining the avoidance contour lines of all components on the to-be-detected jointed board based on the component data on the PCBA, and obtaining the final avoidance contour line of the to-be-detected jointed board based on the avoidance contour lines of all components on the to-be-detected jointed board and the PCBA outer contour line; obtaining the avoidance depth of the component based on the component data on the PCBA and the safety distance between the carrier plate and the component, obtaining the avoidance depth of the to-be-detected jointed board based on the avoidance depth of the component and the preset minimum avoidance depth of the to-be-detected jointed board, and generating a corresponding avoidance groove on the carrier plate based on the final avoidance contour line of the to-be-detected jointed board, the avoidance depth of the to-be-detected jointed board and the layout data of the to-be-detected jointed board; Obtaining a first support area based on the final avoidance contour line of the to-be-detected jointed board and the to-be-detected jointed board data, obtaining a second support area based on the first support area and the to-be-detected jointed board layout data, taking the bottom of the avoidance groove of the carrier plate as a starting surface, stretching the second support area to be the avoidance depth of the to-be-detected jointed board, and stretching the second support area to be an additive to generate a first board surface support on the carrier plate, wherein the number M of to-be-detected jointed boards is obtained according to the to-be-detected jointed board layout data, if M is greater than 1, the first support area is subjected to coordinate