CN-115938323-B - Shift register, gate driving circuit, array substrate and display device

CN115938323BCN 115938323 BCN115938323 BCN 115938323BCN-115938323-B

Abstract

The embodiment of the disclosure provides a shift register, a gate driving circuit, an array substrate and a display device. The shift register comprises a pull-down module, a noise-reducing module and a bootstrap module, wherein the pull-down module is respectively coupled with a second power supply end, a pull-up node, a pull-down node and a control node and is configured to provide signals of the second power supply end for the pull-down node and the control node under the control of the pull-up node, the noise-reducing module is respectively coupled with a first control power supply end, the control node and the pull-down node and is configured to provide signals of the first control power supply end for the control node under the control of the first control power supply end and provide signals of the first control power supply end for the pull-down node under the control of the control node, and the bootstrap module is respectively coupled with the control node and the pull-down node. According to the technical scheme, the noise emission effect is optimized, the problem of reliability and screen flashing of display products is solved, and the service life of the shift register and the competitiveness of the products are improved.

Inventors

ZHU CHUANPING
LI JI
MEI WENJUAN
LIU JIANTAO

Assignees

合肥京东方光电科技有限公司
京东方科技集团股份有限公司

Dates

Publication Date: 20260508
Application Date: 20221028

Claims (9)

1. The array substrate is characterized by comprising a display area, a frame area positioned outside the display area, and a shift register, wherein the shift register is positioned in the frame area; The shift register comprises a pull-up module respectively coupled with an input signal end, a first power end and a pull-up node, configured to provide a signal of the first power end to the pull-up node under the control of the input signal end, a pull-down module respectively coupled with a second power end, the pull-up node, a pull-down node and a control node, configured to provide a signal of the second power end to the pull-down node and the control node under the control of the pull-up node, a noise releasing module respectively coupled with the first control power end, the control node and the pull-down node, configured to provide a signal of the first control power end to the control node under the control of the first control power end, and to provide a signal of the first control power end to the pull-down node under the control of the control node, a reset module respectively coupled with the control node, the pull-up node and the output signal end, configured to provide a signal of the pull-down node and the pull-down node, configured to provide a signal of the second power end to the pull-down node, a reset module respectively coupled with the control node, the pull-down node and the reset module respectively coupled with the control node, the reset module respectively to the pull-down node, the second power node and the reset module respectively coupled with the pull-down node, the reset module and the reset module respectively coupled to the pull-down node, the noise amplifier comprises an output signal terminal, a noise amplifier module, a bootstrap module, a control node and a control node, wherein the output signal terminal is configured to be provided with a signal of the second power supply terminal under the control of the pull-down node, the noise amplifier module comprises a fifth transistor and a ninth transistor, the grid electrode of the ninth transistor is coupled with the first control power supply terminal, the first pole and the second pole of the ninth transistor are respectively coupled with the first control power supply terminal and the control node, the grid electrode of the fifth transistor is coupled with the control node, the first pole of the fifth transistor is coupled with the first control power supply terminal, the second pole of the fifth transistor is coupled with the pull-down node, the bootstrap module comprises a bootstrap capacitor, the first polar plate and the second polar plate of the bootstrap capacitor are respectively coupled with the control node and the pull-down node, the first polar plate of the bootstrap capacitor comprises the grid electrode of the fifth transistor, and the second polar plate of the bootstrap capacitor comprises the second polar plate of the fifth transistor; the array substrate comprises a substrate, a first metal layer, a first insulating layer, a second metal layer and a second metal layer, wherein the first metal layer is positioned on one side of the substrate and comprises a grid electrode of a fifth transistor, the grid electrode of the fifth transistor comprises a third metal wire and a fourth metal wire, the fourth metal wire is connected with one end of the third metal wire, the fourth metal wire is not parallel to the third metal wire, the first insulating layer is positioned on one side of the first metal layer, which is away from the substrate, the second metal layer is positioned on one side of the first insulating layer, which is away from the substrate, and comprises a first electrode and a second electrode of the fifth transistor, the second electrode of the fifth transistor comprises a fifth metal wire and a sixth metal wire, the sixth metal wire is connected with one end of the fifth metal wire, the sixth metal wire is not parallel to the fifth metal wire, the first electrode of the fifth transistor comprises a seventh metal wire, the seventh metal wire is parallel to the fifth metal wire, the fifth metal wire and the fifth metal wire are projected on the front surface of the substrate.
2. The array substrate of claim 1, wherein the array substrate comprises: A substrate; a first metal layer located on one side of the substrate and including a gate of the fifth transistor; the first insulating layer is positioned on one side of the first metal layer, which is away from the substrate; The second metal layer is positioned on one side, away from the substrate, of the first insulating layer and comprises a first pole and a second pole of the fifth transistor, the second pole of the fifth transistor comprises an annular metal wire with an opening, the first pole of the fifth transistor comprises a first metal wire and a second metal wire, the first metal wire is positioned in the annular metal wire, the second metal wire is connected with the first metal wire, and the second metal wire extends out of the opening to the outer side of the annular metal wire.
3. The array substrate of claim 2, wherein the annular metal trace is a rectangular annular metal trace, and the opening is disposed on one rectangular side of the rectangular annular metal trace.
4. The array substrate of claim 2 or 3, further comprising a second insulating layer and a plate pattern, wherein the second insulating layer is located on a side of the second metal layer facing away from the substrate, the plate pattern is located on a side of the second insulating layer facing away from the substrate, a second pole of the fifth transistor is provided with a via hole, the plate pattern penetrates through the second insulating layer and the first insulating layer and is connected with a gate of the fifth transistor through the via hole, an overlapping area exists between the plate pattern and a front projection of the second pole of the fifth transistor on the substrate, and the first plate of the bootstrap capacitor further comprises the plate pattern.
5. The array substrate of claim 1, wherein the bootstrap module comprises a bootstrap capacitor, a first plate and a second plate of the bootstrap capacitor being coupled with the control node and the pull-down node, respectively.
6. The array substrate of claim 1, wherein the shift register comprises at least one of: the pull-down module comprises a sixth transistor and an eighth transistor, wherein the grid electrode of the sixth transistor is coupled with the pull-up node, the first pole and the second pole of the sixth transistor are respectively coupled with the pull-down node and the second power supply terminal, the grid electrode of the eighth transistor is coupled with the pull-up node, and the first pole and the second pole of the eighth transistor are respectively coupled with the control node and the second power supply terminal; The pull-up module comprises a first transistor, wherein the grid electrode of the first transistor is coupled with the input signal end, and the first pole and the second pole of the first transistor are respectively coupled with the first power supply end and the pull-up node; The output module comprises a third transistor and a storage capacitor, wherein the grid electrode of the third transistor is coupled with the pull-up node, the first pole and the second pole of the third transistor are respectively coupled with the clock signal end and the output signal end, and the first polar plate and the second polar plate of the storage capacitor are respectively coupled with the pull-up node and the output signal end; The first reset module comprises a second transistor, the grid electrode of the second transistor is coupled with the reset signal end, and the first pole and the second pole of the second transistor are respectively coupled with the third power end and the pull-up node; The reset control module comprises a tenth transistor, wherein the grid electrode of the tenth transistor is coupled with the pull-down node, and the first pole and the second pole of the tenth transistor are respectively coupled with the second power supply end and the pull-up node; The second reset module includes an eleventh transistor having a gate coupled to the pull-down node, a first pole and a second pole coupled to the second power supply terminal and the output signal terminal, respectively.
7. The array substrate of claim 1, 5 or 6, wherein the shift register further comprises a frame reset module coupled to a second control power supply terminal, the second power supply terminal, the pull-up node and the output signal terminal, respectively, and configured to provide signals of the second power supply terminal to the pull-up node and the output signal terminal under control of the second control power supply terminal.
8. The array substrate of claim 7, wherein the frame reset module comprises a fourth transistor and a seventh transistor, wherein a gate of the fourth transistor is coupled to the second control power supply terminal, a first pole and a second pole of the fourth transistor are coupled to the second power supply terminal and the pull-up node, respectively, a gate of the seventh transistor is coupled to the second control power supply terminal, and a first pole and a second pole of the seventh transistor are coupled to the second power supply terminal and the output signal terminal, respectively.
9. A display device comprising the array substrate of any one of claims 1-8.

Description

Shift register, gate driving circuit, array substrate and display device Technical Field The disclosure relates to the technical field of display, and in particular relates to a shift register, a gate driving circuit, an array substrate and a display device. Background With the increasing maturity of display technology, the demand of small-size display products for narrow frame and high frequency display is increasing. The GOA (Gate on Array) technology integrates the grid switch driving circuit on the array substrate of the display panel, so that the narrow frame, low cost and wide application in small-size display products are realized. In a narrow-frame display product, GOA wiring space is limited, so that part of transistors are smaller in size due to insufficient wiring space, the problem of reliability and screen flashing of the display product is caused, and the product competitiveness is reduced. Disclosure of Invention Embodiments of the present disclosure provide a shift register, a gate driving circuit, an array substrate, and a display device, to solve or alleviate one or more technical problems in the prior art. As a first aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a shift register, including: The pull-up module is respectively coupled with the input signal end, the first power end and the pull-up node and is configured to provide a signal of the first power end for the pull-up node under the control of the input signal end; the pull-down module is respectively coupled with the second power supply end, the pull-up node, the pull-down node and the control node and is configured to provide signals of the second power supply end for the pull-down node and the control node under the control of the pull-up node; The noise amplifier module is respectively coupled with the first control power supply end, the control node and the pull-down node and is configured to provide a signal of the first control power supply end for the control node under the control of the first control power supply end and provide a signal of the first control power supply end for the pull-down node under the control of the control node; the bootstrap module is respectively coupled with the control node and the pull-down node; The output module is respectively coupled with the clock signal end, the pull-up node and the output signal end and is configured to provide signals of the clock signal end for the output signal end under the control of the pull-up node; The first reset module is coupled with the reset signal end, the third power end and the pull-up node respectively and is configured to provide a signal of the third power end for the pull-up node under the control of the reset signal end; the reset control module is respectively coupled with the pull-down node, the second power supply end and the pull-up node and is configured to provide a signal of the second power supply end for the pull-up node under the control of the pull-down node; And the second reset module is respectively coupled with the pull-down node, the second power supply end and the output signal end and is configured to provide a signal of the second power supply end for the output signal end under the control of the pull-down node. In one embodiment, the bootstrap module includes a bootstrap capacitor having first and second plates coupled to the control node and the pull-down node, respectively. In one embodiment, the noise amplifier includes a fifth transistor and a ninth transistor, a gate of the ninth transistor is coupled to the first control power terminal, a first pole and a second pole of the ninth transistor are respectively coupled to the first control power terminal and the control node, a gate of the fifth transistor is coupled to the control node, a first pole of the fifth transistor is coupled to the first control power terminal, and a second pole of the fifth transistor is coupled to the pull-down node. In one embodiment, the bootstrap module includes a bootstrap capacitor, a first plate and a second plate of the bootstrap capacitor are coupled to the control node and the pull-down node, respectively, the first plate of the bootstrap capacitor includes a gate of the fifth transistor, and the second plate of the bootstrap capacitor includes a second plate of the fifth transistor. In one embodiment, at least one of the following is included: The pull-down module comprises a sixth transistor and an eighth transistor, wherein the grid electrode of the sixth transistor is coupled with the pull-up node, the first pole and the second pole of the sixth transistor are respectively coupled with the pull-down node and the second power supply terminal, the grid electrode of the eighth transistor is coupled with the pull-up node, and the first pole and the second pole of the eighth transistor are respectively coupled with the control node and the second power supply terminal; The pull-up mod