CN-115938917-B - Method for manufacturing semiconductor structure

Abstract

The invention discloses a manufacturing method of a semiconductor structure, which comprises the following steps. A substrate is provided. The substrate has a first region and a second region. A stacked structure is formed on the substrate in the first region. The stacked structure comprises a first dielectric layer, a charge storage layer, a second dielectric layer, a first conductor layer and a first hard mask layer. A layer of dielectric material is formed on the substrate in the second region. A second conductor layer is formed over the dielectric material layer in the second region. A first patterned photoresist layer is formed, wherein the first patterned photoresist layer exposes the first hard mask layer in the first region and a portion of the dielectric material layer in the second region. The first hard mask layer exposed by the first patterned photoresist layer and a portion of the dielectric material layer exposed by the first patterned photoresist layer are removed using the first patterned photoresist layer as a mask.

Inventors

• GONG WENWEN
• HAN XIAOFEI
• Lin Chaoyu
• LIAO HONG
• QIAN JUN

Assignees

• 联华电子股份有限公司

Dates

Publication Date

20260512

Application Date

20210720

Claims (20)

1. 1. A method of fabricating a semiconductor structure, comprising: Providing a substrate, wherein the substrate is provided with a first area and a second area; forming a stacked structure on the substrate in the first region, wherein the stacked structure comprises: A first dielectric layer on the substrate; a charge storage layer on the first dielectric layer; a second dielectric layer on the charge storage layer; A first conductor layer on the second dielectric layer, and A first hard mask layer on the first conductor layer; forming a layer of dielectric material on the substrate in the second region; forming a second conductor layer on the dielectric material layer in the second region; Forming a first patterned photoresist layer exposing a portion of the dielectric material layer in the first region and the first hard mask layer in the second region, and And removing the first hard mask layer exposed by the first patterned photoresist layer and a portion of the dielectric material layer exposed by the first patterned photoresist layer using the first patterned photoresist layer as a mask, wherein the first patterned photoresist layer directly contacts the top surface of the second conductor layer.
2. 2. The method of claim 1, wherein the removing the first hard mask layer exposed by the first patterned photoresist layer and the portion of the dielectric material layer exposed by the first patterned photoresist layer comprises performing an etching process.
3. 3. The method of claim 2, wherein a ratio of an etching rate of the first hard mask layer to an etching rate of the dielectric material layer in the etching process is in a range of 1.5 to 1.
4. 4. The method of claim 2, wherein a ratio of an etching rate of the first hard mask layer to an etching rate of the dielectric material layer in the etching process is in a range of 1.3 to 1.
5. 5. The method of manufacturing a semiconductor structure of claim 2, wherein the etch fabrication process comprises a dry etch fabrication process.
6. 6. The method of manufacturing a semiconductor structure of claim 1, wherein said first patterned photoresist layer covers a portion of said first hard mask layer.
7. 7. The method of manufacturing a semiconductor structure as recited in claim 6, wherein after removing the first hard mask layer exposed by the first patterned photoresist layer, a portion of the first hard mask layer covered by the first patterned photoresist layer remains.
8. 8. The method of manufacturing a semiconductor structure of claim 1, wherein the stacked structure further comprises: a second hard mask layer between the first hard mask layer and the first conductor layer, wherein After removing the first hard mask layer exposed by the first patterned photoresist layer, the first patterned photoresist layer exposes the second hard mask layer.
9. 9. The method of manufacturing a semiconductor structure of claim 8, further comprising: The second hard mask layer exposed by the first patterned photoresist layer is removed using the first patterned photoresist layer as a mask.
10. 10. The method of manufacturing a semiconductor structure of claim 9, wherein the first patterned photoresist layer covers a portion of the second hard mask layer.
11. 11. The method of manufacturing a semiconductor structure of claim 10, wherein after removing the second hard mask layer exposed by the first patterned photoresist layer, a portion of the second hard mask layer covered by the first patterned photoresist layer remains.
12. 12. The method of manufacturing a semiconductor structure of claim 1, further comprising: after removing a portion of the dielectric material layer exposed by the first patterned photoresist layer, two doped regions are formed in the substrate on both sides of the second conductor layer using the first patterned photoresist layer as a mask.
13. 13. The method of manufacturing a semiconductor structure of claim 12, further comprising: after forming the two doped regions, the first patterned photoresist layer is removed.
14. 14. The method of manufacturing a semiconductor structure of claim 1, wherein the method of forming the second conductor layer comprises: Forming a layer of conductor material over the layer of dielectric material in the second region; Conformally forming a hard mask material layer on the stacked structure and the conductor material layer; Forming a second patterned photoresist layer on the hard mask material layer in the second region, wherein the second patterned photoresist layer is not directly over the stacked structure in the first region; removing a portion of the hard mask material layer exposed by the second patterned photoresist layer to form a second hard mask layer, and Portions of the conductor material layer in the second region exposed by the second hard mask layer are removed.
15. 15. The method of manufacturing a semiconductor structure of claim 14, wherein a height of the first hard mask layer in the first region is reduced simultaneously during removing a portion of the conductor material layer in the second region exposed by the second hard mask layer.
16. 16. The method of manufacturing a semiconductor structure of claim 1, wherein the first patterned photoresist layer covers the second conductor layer.
17. 17. The method of manufacturing a semiconductor structure of claim 1, further comprising: and forming a spacer on the side wall of the stacked structure.
18. 18. The method of manufacturing a semiconductor structure of claim 1, further comprising: An isolation structure is formed in the substrate in the first region.
19. 19. The method of manufacturing a semiconductor structure of claim 18, wherein a portion of the stacked structure is located directly above the isolation structure.
20. 20. The method of manufacturing a semiconductor structure of claim 1, wherein the first region comprises a memory region and the second region comprises a logic element region.

Description

Method for manufacturing semiconductor structure Technical Field The present invention relates to a method for manufacturing a semiconductor structure, and more particularly, to a method for manufacturing a semiconductor structure with reduced complexity and cost. Background With the progress of semiconductor technology, semiconductor fabrication processes are becoming more and more complex, and fabrication costs are increasing. In addition, when the chip has different device regions, the complexity of the manufacturing process is further increased. Therefore, how to reduce the complexity and cost of the manufacturing process is the goal of continuous efforts. Disclosure of Invention The invention provides a manufacturing method of a semiconductor structure, which can reduce the complexity of manufacturing process and manufacturing cost. The invention provides a manufacturing method of a semiconductor structure, which comprises the following steps. A substrate is provided. The substrate has a first region and a second region. A stacked structure is formed on the substrate in the first region. The stacked structure comprises a first dielectric layer, a charge storage layer, a second dielectric layer, a first conductor layer and a first hard mask layer. The first dielectric layer is located on the substrate. The charge storage layer is located on the first dielectric layer. The second dielectric layer is located on the charge storage layer. The first conductor layer is positioned on the second dielectric layer. The first hard mask layer is located on the first conductor layer. A layer of dielectric material is formed on the substrate in the second region. A second conductor layer is formed over the dielectric material layer in the second region. A first patterned photoresist layer is formed, wherein the first patterned photoresist layer exposes the first hard mask layer in the first region and a portion of the dielectric material layer in the second region. The first hard mask layer exposed by the first patterned photoresist layer and a portion of the dielectric material layer exposed by the first patterned photoresist layer are removed using the first patterned photoresist layer as a mask. In an embodiment of the present invention, in the method for manufacturing a semiconductor structure, the removing method of the first hard mask layer exposed by the first patterned photoresist layer and the portion of the dielectric material layer exposed by the first patterned photoresist layer may include performing an etching process. In an embodiment of the present invention, in the method for manufacturing a semiconductor structure, a ratio of an etching rate of the first hard mask layer to an etching rate of the dielectric material layer in the etching process may be in a range of 1.5 to 1. In an embodiment of the present invention, in the method for manufacturing a semiconductor structure, a ratio of an etching rate of the first hard mask layer to an etching rate of the dielectric material layer in the etching process may be in a range of 1.3 to 1. In an embodiment of the invention, in the method for manufacturing a semiconductor structure, the etching process is, for example, a dry etching process. In an embodiment of the present invention, in the method for manufacturing a semiconductor structure, the first patterned photoresist layer may cover a portion of the first hard mask layer. In an embodiment of the present invention, in the method for manufacturing a semiconductor structure, after removing the first hard mask layer exposed by the first patterned photoresist layer, a portion of the first hard mask layer covered by the first patterned photoresist layer may be left. In an embodiment of the present invention, in the method for manufacturing a semiconductor structure, the stacked structure may further include a second hard mask layer. The second hard mask layer is located between the first hard mask layer and the first conductor layer. After removing the first hard mask layer exposed by the first patterned photoresist layer, the first patterned photoresist layer may expose the second hard mask layer. In accordance with an embodiment of the present invention, the method for manufacturing a semiconductor structure may further include the following steps. The second hard mask layer exposed by the first patterned photoresist layer is removed using the first patterned photoresist layer as a mask. In an embodiment of the present invention, in the method for manufacturing a semiconductor structure, the first patterned photoresist layer may cover a portion of the second hard mask layer. In an embodiment of the present invention, in the method for manufacturing a semiconductor structure, after removing the second hard mask layer exposed by the first patterned photoresist layer, a portion of the second hard mask layer covered by the first patterned photoresist layer may be left. According to an embodiment of the presen