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CN-115939157-B - Semiconductor element, packaging structure of semiconductor element and packaging method of semiconductor element

CN115939157BCN 115939157 BCN115939157 BCN 115939157BCN-115939157-B

Abstract

The invention discloses a semiconductor element, a packaging structure of the semiconductor element and a packaging method of the packaging structure, wherein the semiconductor element comprises a substrate, a functional structure formed in the substrate and a welding pad connected with the functional structure, the functional structure comprises a shallow groove isolation layer with a mesh structure, the shallow groove isolation layer does not extend to the welding pad, or the shallow groove isolation layer extends to the welding pad and belongs to a part of the welding pad, and meshes of the shallow groove isolation layer meet that the mesh width is 2.29-2.49 mu m. The semiconductor element of the invention can solve the problem of STI (shallow trench isolation) layering in the subsequent packaging process due to the existence of the STI.

Inventors

  • WANG XINQIN

Assignees

  • 苏州晶方半导体科技股份有限公司

Dates

Publication Date
20260512
Application Date
20221122

Claims (10)

  1. 1. The semiconductor element is characterized by comprising a substrate, a functional structure formed in the substrate and a welding pad connected with the functional structure, wherein the welding pad and the projection of the functional structure in the thickness direction of the substrate are not overlapped, the functional structure comprises a shallow groove isolation layer with a mesh structure, the shallow groove isolation layer extends to the welding pad and belongs to a part of the welding pad, and the mesh width of the shallow groove isolation layer is 2.29-2.49 mu m.
  2. 2. The semiconductor device according to claim 1, wherein the shallow trench isolation layer has a mesh depth ranging from 0.2 μm to 0.4 μm and a mesh gap ranging from 2.76 μm to 2.96 μm.
  3. 3. The semiconductor device of claim 1, wherein the functional structure further comprises a polysilicon layer extending to and being part of the bond pad, and the polysilicon layer is formed on the shallow trench isolation layer.
  4. 4. The semiconductor device of claim 3, wherein said polysilicon layer comprises a plurality of polysilicon units arranged in an array, each of said polysilicon units being formed on a mesh gap of said shallow trench isolation layer.
  5. 5. The semiconductor device of claim 3, wherein the bonding pad comprises a metal layer comprising a plurality of sub-metal layers disposed at intervals, adjacent ones of the sub-metal layers being electrically connected.
  6. 6. The semiconductor device according to claim 5, wherein a dielectric layer is provided between adjacent ones of the sub-metal layers.
  7. 7. The semiconductor device of claim 6, wherein metal plugs are formed in said dielectric layer, and wherein adjacent ones of said sub-metal layers are electrically connected by said metal plugs.
  8. 8. The semiconductor device according to claim 1, wherein the shallow trench isolation layer has a mesh having a width of 2.39 μm, a depth of 0.3 μm, and a mesh gap of 2.86 μm.
  9. 9. A package structure of a semiconductor element, comprising: the semiconductor device according to any one of claims 1 to 8, wherein the solder bump is disposed on a surface of the semiconductor device, and the rewiring layer is electrically connected between the solder bump and the solder pad through a via hole formed in the semiconductor device, wherein the via hole exposes the solder pad.
  10. 10. A packaging method of a packaging structure of a semiconductor element, comprising: Providing a wafer with a plurality of semiconductor elements according to any one of claims 1-8 arranged in an array; Forming a through hole penetrating through the bonding pad from the surface of the semiconductor element; Forming a passivation layer on the side wall of the through hole and the surface of the semiconductor element; Forming a rewiring layer covering the side wall, the bottom wall and the surface of the semiconductor element; and forming a welding bump electrically connected with the rewiring layer on the rewiring layer.

Description

Semiconductor element, packaging structure of semiconductor element and packaging method of semiconductor element Technical Field The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor device, a package structure of the semiconductor device, and a method for packaging the package structure of the semiconductor device. Background In the prior art, CMOS image sensors (CMOS Image Sensor, CIS) are being developed toward high speed, large pixels and low cost, and wafer level packaging technology has been receiving attention in recent years due to its advantages of miniaturization and low cost. CIS can be divided into three structures, front-lit (Front Side Illuminated, FSI), back-lit (Back Side Illuminated, BSI), stacked (Stack). A shallow trench isolation process is used in a 3D Stack (Stack) CIS, including STACK WAFER. Shallow trench isolation, shallow trench isolation, STI for short, is commonly used for processes below 0.25um by forming a trench after deposition, patterning, etching silicon using a silicon nitride mask, and filling the trench with a deposited oxide for isolation from silicon. In the packaging stage, the Low-k material (dielectric layer) in the STACK WAFER metal Pad is very fragile, which presents a great challenge for packaging. To meet the emerging CIS wafer level packaging, vertical via packaging techniques are often employed. The technology can meet the packaging requirements of chips with more I/O numbers, higher reliability requirements and more complex metal Pad structures. However, in actual packaging, due to the design of STI, delamination phenomenon is found at STI after etching the via hole, and referring to fig. 1, where a is a through silicon via hole, b is a shallow trench isolation layer, c is a metal layer of a pad, and h is a delamination gap. This makes the subsequently formed metal conductive lead (re-wiring layer) not well electrically connected to the pad, degrading the performance of the product. The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art. Disclosure of Invention The invention aims to provide a semiconductor element, a packaging structure of the semiconductor element and a packaging method of the packaging structure of the semiconductor element, which can solve the problem of STI (shallow trench isolation) layering in the subsequent packaging process due to the existence of the STI. In order to achieve the above object, an embodiment of the present invention provides a semiconductor element including a substrate, a functional structure formed in the substrate, and a bonding pad connected to the functional structure, wherein the functional structure includes a shallow trench isolation layer having a mesh structure, the shallow trench isolation layer does not extend to the bonding pad, or the shallow trench isolation layer extends to the bonding pad and is part of the bonding pad, wherein a mesh width of the shallow trench isolation layer is in a range of 2.29 μm to 2.49 μm. In one or more embodiments of the invention, the mesh of the shallow trench isolation layer satisfies a mesh depth in a range of 0.2 μm to 0.4 μm and a mesh gap of 2.76 μm to 2.96 μm. In one or more embodiments of the present invention, the shallow trench isolation layer does not extend to the bonding pad, and the functional structure further includes a polysilicon layer that does not extend to the bonding pad. In one or more embodiments of the present invention, the shallow trench isolation layer extends to and is part of the bonding pad, the functional structure further includes a polysilicon layer extending to and is part of the bonding pad, and the polysilicon layer is formed on the shallow trench isolation layer. In one or more embodiments of the present invention, the polysilicon layer includes a plurality of polysilicon units arranged in an array, each of the polysilicon units being formed on a mesh gap of the shallow trench isolation layer. In one or more embodiments of the present invention, the bonding pad includes a metal layer, where the metal layer includes a plurality of sub-metal layers disposed at intervals, and adjacent sub-metal layers are electrically connected to each other. In one or more embodiments of the present invention, a dielectric layer is disposed between adjacent sub-metal layers. In one or more embodiments of the present invention, a metal plug is formed in the dielectric layer, and adjacent sub-metal layers are electrically connected through the metal plug. In one or more embodiments of the present invention, the shallow trench isolation layer extends to the pad, and the mesh of the shallow trench isolation layer satisfies a width of 2.39 μm, a depth of