CN-115951932-B - Techniques for command sequence adjustment

Abstract

The present disclosure is directed to techniques for command sequence adjustment. The memory system or host system may adjust the order of the command sets in the queue, such as by determining whether each command of the subset corresponds to the same size of data, if the memory system or host system determines that the subset of commands in the queue is part of a test pattern. The command set may be reordered such that the subset of commands associated with the test pattern are consecutive or back-to-back. In some cases, the subset of commands associated with the test pattern may be reordered such that logical addresses (e.g., logical block addresses) of the subset of commands are consecutive.

Inventors

• BI YANHUA

Assignees

• 美光科技公司

Dates

Publication Date

20260512

Application Date

20220930

Priority Date

20211008

Claims (20)

1. 1. An apparatus for command sequence adjustment, comprising: memory device, and A controller coupled with the memory device and configured to cause the apparatus to: receiving a command set at a memory system; Storing the command set in a queue according to a first sequence based at least in part on receiving the command set; Determining whether a subset of commands in the set of commands are associated with a test pattern, wherein determining that the subset of commands are associated with the test pattern is based at least in part on a respective size of data associated with each command of the subset of commands; Configuring a second sequence of the set of commands in the queue based at least in part on determining that the subset of commands is associated with the test pattern, the second sequence based at least in part on a respective logical address associated with each command of the subset of commands, and The subset of commands is executed according to the second sequence as part of the test pattern.
2. 2. The apparatus of claim 1, wherein configuring the second sequence is configured to cause the apparatus to: the order of the subset of commands in the queue is adjusted such that a first logical address associated with a first command in the queue is smaller than a second logical address associated with a second command in the queue, wherein the second command is executed according to the second sequence after the first command.
3. 3. The device of claim 1, wherein the subset of execution commands is configured to cause the device to: First data associated with at least one command of the subset of commands is written to a first block based at least in part on determining that the subset of commands is associated with the test pattern.
4. 4. The apparatus of claim 3, wherein the controller is further configured to cause the apparatus to: a second subset of commands in the command set is executed, the second subset being different from the subset.
5. 5. The apparatus of claim 4, wherein the second subset of execution commands is configured to cause the apparatus to: second data associated with at least one command of the second subset of commands is written to a second block of memory cells different from the first block.
6. 6. The apparatus of claim 1, wherein the subset of commands comprises one or more write commands, each write command of the one or more write commands identifying data of a same size.
7. 7. The apparatus of claim 1, wherein determining that the subset of commands in the set of commands are associated with the test pattern is based at least in part on the respective size of data associated with each command of the subset meeting a threshold.
8. 8. The apparatus of claim 1, wherein determining that the subset of commands in the set of commands is associated with the test pattern is based at least in part on a number of commands of the subset meeting a threshold.
9. 9. An apparatus for command sequence adjustment, comprising: memory device, and A controller coupled with the memory device and configured to cause the apparatus to: receiving a command set at a memory system; Storing the command set in a queue according to a first sequence based at least in part on receiving the command set; determining whether a subset of commands in the command set are associated with a test pattern; Configuring a second sequence of the set of commands in the queue based at least in part on determining that the subset of commands is associated with the test pattern, the second sequence based at least in part on respective logical addresses associated with each command of the subset of commands; executing the subset of commands according to the second sequence as part of the test pattern; writing first data associated with at least one command of the subset of commands to a first block based at least in part on determining that the subset of commands is associated with the test pattern; receiving a demap command identifying data associated with the subset of commands, and The first data is erased from the first block based at least in part on receiving the unmap command.
10. 10. An apparatus for command sequence adjustment, comprising Memory device, and A controller coupled with the memory device and configured to cause the apparatus to: receiving a command set at a memory system; Storing the command set in a queue according to a first sequence based at least in part on receiving the command set; determining whether a subset of commands in the command set are associated with a test pattern; Configuring a second sequence of the set of commands in the queue based at least in part on determining that the subset of commands is associated with the test pattern, the second sequence based at least in part on respective logical addresses associated with each command of the subset of commands; Executing said subset of commands according to said second sequence as part of said test pattern, and The test mode is determined to end based at least in part on the second subset of commands satisfying the threshold number of commands.
11. 11. The apparatus of claim 10, wherein determining to end the test mode is further based at least in part on the second subset of commands comprises a demap command.
12. 12. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: receiving a command set at a memory system; Storing the command set in a queue according to a first sequence based at least in part on receiving the command set; Determining whether a subset of commands in the set of commands are associated with a test pattern, wherein determining that the subset of commands are associated with the test pattern is based at least in part on a respective size of data associated with each command of the subset of commands; Configuring a second sequence of the set of commands in the queue based at least in part on determining that the subset of commands is associated with the test pattern, the second sequence based at least in part on a respective logical address associated with each command of the subset of commands, and The subset of commands is executed according to the second sequence as part of the test pattern.
13. 13. The non-transitory computer-readable medium of claim 12, wherein the instructions to configure the second sequence are executable by the processor to: the order of the subset of commands in the queue is adjusted such that a first logical address associated with a first command in the queue is smaller than a second logical address associated with a second command in the queue, wherein the second command is executed according to the second sequence after the first command.
14. 14. The non-transitory computer-readable medium of claim 12, wherein the instructions to execute the subset of commands are executable by the processor to: First data associated with at least one command of the subset of commands is written to a first block based at least in part on determining that the subset of commands is associated with the test pattern.
15. 15. The non-transitory computer-readable medium of claim 14, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to execute a second subset of commands in the command set, the second subset being different than the subset.
16. 16. The non-transitory computer-readable medium of claim 15, wherein the instructions to execute the second subset of commands are executable by the processor to: second data associated with at least one command of the second subset of commands is written to a second block of memory cells different from the first block.
17. 17. The non-transitory computer-readable medium of claim 12, wherein the subset of commands comprises one or more write commands, each write command of the one or more write commands identifying data of a same size.
18. 18. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, further cause the electronic device to: receiving a command set at a memory system; Storing the command set in a queue according to a first sequence based at least in part on receiving the command set; determining whether a subset of commands in the command set are associated with a test pattern; Configuring a second sequence of the set of commands in the queue based at least in part on determining that the subset of commands is associated with the test pattern, the second sequence based at least in part on respective logical addresses associated with each command of the subset of commands; executing the subset of commands according to the second sequence as part of the test pattern; Writing first data associated with at least one command of the subset of commands to a first block based at least in part on determining that the subset of commands is associated with the test pattern, and Receiving a demap command identifying data associated with the subset of commands, and The first data is erased from the first block based at least in part on receiving the unmap command.
19. 19. A method for command sequence adjustment, comprising: receiving a command set at a memory system; Storing the command set in a queue according to a first sequence based at least in part on receiving the command set; Determining whether a subset of commands in the set of commands are associated with a test pattern, wherein determining that the subset of commands are associated with the test pattern is based at least in part on a respective size of data associated with each command of the subset of commands; Configuring a second sequence of the set of commands in the queue based at least in part on determining that the subset of commands is associated with the test pattern, the second sequence based at least in part on a respective logical address associated with each command of the subset of commands, and The subset of commands is executed according to the second sequence as part of the test pattern.
20. 20. The method of claim 19, wherein configuring the second sequence comprises: the order of the subset of commands in the queue is adjusted such that a first logical address associated with a first command in the queue is smaller than a second logical address associated with a second command in the queue, wherein the second command is executed according to the second sequence after the first command.

Description

Techniques for command sequence adjustment Cross reference to This patent application claims priority from U.S. patent application Ser. No. 17/497,610 entitled "technique for command sequence adjustment (TECHNIQUES FOR COMMAND SEQUENCE ADJUSTMENT)", filed on even date 10/8 of 2021, assigned to the present assignee and expressly incorporated herein by reference. Technical Field The technical field relates to techniques for command sequence adjustment. Background Memory devices are widely used to store information in a variety of electronic devices, such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory device to various states. For example, a binary memory cell may be programmed to one of two support states, often corresponding to a logic 1 or a logic 0. In some examples, a single memory cell may support more than two possible states, and a memory cell may store either of the two possible states. To access information stored by the memory device, the component may read or sense the state of one or more memory cells within the memory device. To store information, a component may write or program one or more memory cells within a memory device to respective states. There are various types of memory devices including magnetic hard disk, random Access Memory (RAM), read Only Memory (ROM), dynamic RAM (DRAM), synchronous Dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase Change Memory (PCM), three-dimensional cross point memory (3D cross point), NOR and NAND (NAND) memory devices, and the like. The memory device may be volatile or nonvolatile. Unless periodically refreshed by an external power source, volatile memory cells (e.g., DRAM cells) may lose their programmed state over time. Nonvolatile memory cells (e.g., NAND memory cells) may maintain their programmed state for a long period of time even in the absence of an external power source. Disclosure of Invention An apparatus is described. The apparatus may include a memory device, and a controller coupled with the memory device and configured to cause the apparatus to receive a set of commands at a memory system, store the set of commands in a queue according to a first sequence based on receiving the set of commands, determine whether a subset of commands in the set of commands are associated with a test pattern, configure a second sequence of the set of commands in the queue based on determining that the subset of commands are associated with the test pattern, the second sequence based on respective logical addresses associated with each command of the subset of commands, and execute the subset of commands according to the second sequence as part of the test pattern. A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to receive a set of commands at a memory system, store the set of commands in a queue according to a first sequence based on receiving the set of commands, determine whether a subset of commands in the set of commands are associated with a test pattern, configure a second sequence of the set of commands in the queue based on determining that the subset of commands are associated with the test pattern, the second sequence based on respective logical addresses associated with each command of the subset of commands, and execute the subset of commands according to the second sequence as part of the test pattern. A method is described. The method may include receiving a set of commands at a memory system, storing the set of commands in a queue according to a first sequence based on receiving the set of commands, determining whether a subset of commands in the set of commands are associated with a test pattern, configuring a second sequence of the set of commands in the queue based on determining that the subset of commands are associated with the test pattern, the second sequence based on respective logical addresses associated with each command of the subset of commands, and executing the subset of commands according to the second sequence as part of the test pattern. Drawings Fig. 1 illustrates an example of a system that supports techniques for command sequence adjustment according to examples as disclosed herein. Fig. 2 illustrates an example of a system that supports techniques for command sequence adjustment according to examples as disclosed herein. FIG. 3 illustrates an example of a process flow supporting techniques for command sequence adjustment according to examples as disclosed herein. FIG. 4 illustrates an example of a process flow supporting techniques for command sequence adjustment according to examples as disclosed herein. FIG. 5 shows a block diagram of a memory sys