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CN-115964321-B - Data transmission device and data transmission method

CN115964321BCN 115964321 BCN115964321 BCN 115964321BCN-115964321-B

Abstract

The disclosure provides a data transmission device and a data transmission method, relates to the technical field of communication, and particularly relates to the field of chips. The device comprises a master device and a plurality of slave devices, wherein the master device comprises a first chip selection interface and is configured to generate chip selection analog signal values, the input end of each analog-to-digital conversion circuit is electrically connected with the first chip selection interface, each analog-to-digital conversion circuit is configured to convert the chip selection analog signal values into chip selection digital signal values, each slave device comprises a second chip selection interface, each second chip selection interface is electrically connected with the output end of the corresponding analog-to-digital conversion circuit of the slave device, and each slave device is configured to establish communication connection with the master device under the condition that the chip selection digital signal values received by the second chip selection interface are valid chip selection digital signal values.

Inventors

  • YAO FENG

Assignees

  • 北京百度网讯科技有限公司

Dates

Publication Date
20260512
Application Date
20211011

Claims (10)

  1. 1. A data transmission apparatus comprising: a master device comprising a first slice interface, the master device configured to generate a slice analog signal value; A plurality of analog-to-digital conversion circuits, each of which has an input terminal electrically connected to the first chip-select interface, each of which is configured to convert the chip-select analog signal value into a chip-select digital signal value, and Each slave device comprises a second chip selection interface, each second chip selection interface is electrically connected with the output end of the analog-to-digital conversion circuit corresponding to the slave device, and each slave device is configured to establish communication connection with the master device when the chip selection digital signal value received by the second chip selection interface is a valid chip selection digital signal value; wherein each analog-to-digital conversion circuit includes: A window comparison sub-circuit configured to generate the valid chip-select digital signal value representing a chip-select digital signal value of a first level if the chip-select analog signal value received at an input of the window comparison sub-circuit is greater than a first reference analog signal value corresponding to the window comparison sub-circuit and less than a second reference analog signal value; the window comparison subcircuit includes: The first comparator comprises a first co-directional input end and a first reverse input end, the first reverse input end is electrically connected with the first chip selection interface, and the first co-directional input end is used for inputting a first reference analog signal value corresponding to the window comparison sub-circuit; The second comparator comprises a second non-inverting input end and a second inverting input end, the second non-inverting input end is electrically connected with the first chip selection interface, and the second inverting input end is used for inputting a second reference analog signal value corresponding to the window comparison sub-circuit; The first input end of the voltage limiting unit is electrically connected with the output end of the first comparator, the second input end of the voltage limiting unit is electrically connected with the output end of the second comparator, the output end of the voltage limiting unit is electrically connected with the second chip selection interface of the slave device, and the voltage limiting unit is configured to generate the effective chip selection digital signal value according to the output value of the first comparator and the output value of the second comparator.
  2. 2. The apparatus of claim 1, wherein, The window comparison sub-circuit is further configured to generate a non-valid chip-select digital signal value if the chip-select analog signal value received at the input of the window comparison sub-circuit is less than or equal to the first reference analog signal value or greater than or equal to the second reference analog signal value, wherein the non-valid chip-select digital signal value is used to characterize a chip-select digital signal value of a second level.
  3. 3. The apparatus of claim 2, wherein, The voltage limiting unit is further configured to generate the non-valid chip select digital signal value according to the output value of the first comparator and the output value of the second comparator.
  4. 4. A device according to claim 3, wherein the voltage limiting unit comprises: a first switching element, one end of which is electrically connected with the output end of the first comparator; A second switching element having one end electrically connected to the output end of the second comparator, and And a transistor configured to output the valid chip select digital signal value if the transistor is in an off state and to output the non-valid chip select digital signal value if the transistor is in a saturated state.
  5. 5. A device according to claim 3, wherein the voltage limiting unit comprises: And the first input end of the logic gate element is electrically connected with the output end of the first comparator, and the second input end of the logic gate element is electrically connected with the output end of the second comparator.
  6. 6. The apparatus of any one of claims 1-5, wherein the master device comprises: The digital-to-analog conversion unit is configured to generate the chip selection analog signal value according to a preset digital signal value based on a preset chip selection rule.
  7. 7. The apparatus of any one of claims 1-5, wherein the master device comprises: A pulse width modulation unit configured to generate a pulse width modulation signal value based on a preset chip selection rule, and A filtering unit configured to convert the pulse width modulated signal values into the chip select analog signal values.
  8. 8. A data transmission method for the data transmission device according to any one of claims 1 to 7, comprising: The main equipment generates a chip selection analog signal value; Each of the plurality of analog-to-digital conversion circuits converting the chip-select analog signal value to a chip-select digital signal value, and Each of the plurality of slave devices establishes a communication connection with the master device if the received chip select digital signal value is a valid chip select digital signal value.
  9. 9. The method of claim 8, wherein each of the analog-to-digital conversion circuits comprises a window comparison sub-circuit; each of the analog-to-digital conversion circuits of the plurality of analog-to-digital conversion circuits converts the chip-select analog signal value to a chip-select digital signal value, comprising: Each of the plurality of window comparison sub-circuits generates an effective chip-select digital signal value in the case that the received chip-select analog signal value is greater than a first reference analog signal value corresponding to the window comparison sub-circuit and less than a second reference analog signal value, wherein the effective chip-select digital signal value is used for representing a chip-select digital signal value of a first level, and And generating a non-valid chip-selection digital signal value under the condition that the received chip-selection analog signal value is smaller than or equal to the first reference analog signal value or larger than or equal to the second reference analog signal value, wherein the non-valid chip-selection digital signal value is used for representing the chip-selection digital signal value of the second level.
  10. 10. The method according to claim 8 or 9, wherein the master device comprises a digital-to-analog conversion unit; the master device generates a chip select analog signal value comprising: the digital-to-analog conversion unit generates the chip selection analog signal value according to a preset digital signal value based on a preset chip selection rule.

Description

Data transmission device and data transmission method Technical Field The present disclosure relates to the field of communications technologies, and in particular, to the field of chips. And more particularly, to a data transmission apparatus and a data transmission method. Background Data transmission between multiple devices may be accomplished based on a communication protocol. Before data transmission can be achieved, a communication connection between every two devices needs to be established. The communication protocol may include a serial peripheral interface (SERIAL PERIPHERAL INTERFACE, SPI) protocol or an integrated circuit bus (Inter-IntegratedCircuit, IIC) protocol, or the like. For example, the plurality of devices includes a master device and a plurality of slave devices, which may enable data transfer between the master device and the plurality of slave devices based on a serial peripheral interface protocol. Disclosure of Invention The present disclosure provides a data transmission apparatus and a data transmission method. According to an aspect of the disclosure, there is provided a data transmission apparatus, including a master device including a first chip select interface, the master device being configured to generate a chip select analog signal value, a plurality of analog-to-digital conversion circuits, each of which has an input terminal electrically connected to the first chip select interface, each of which is configured to convert the chip select analog signal value into a chip select digital signal value, and a plurality of slave devices, each of which includes a second chip select interface, each of which is electrically connected to an output terminal of an analog-to-digital conversion circuit corresponding to the slave device, each of which is configured to establish a communication connection with the master device in a case where the chip select digital signal value received by the second chip select interface is a valid chip select digital signal value. According to another aspect of the present disclosure, there is provided a data transmission method for a data transmission apparatus as described above, including a master device generating a chip-select analog signal value, each of a plurality of analog-to-digital conversion circuits converting the chip-select analog signal value into a chip-select digital signal value, and each of a plurality of slave devices establishing a communication connection with the master device in a case where the received chip-select digital signal value is a valid chip-select digital signal value. It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification. Drawings The drawings are for a better understanding of the present solution and are not to be construed as limiting the present disclosure. Wherein: fig. 1 schematically shows a schematic structure of a data transmission device; Fig. 2A schematically illustrates a structural diagram of a data transmission apparatus according to an embodiment of the present disclosure; FIG. 2B schematically illustrates a schematic diagram of a window comparison subcircuit, according to an embodiment of the present disclosure; fig. 2C schematically illustrates a structural diagram of a data transmission apparatus in the case of n=5 according to an embodiment of the present disclosure; FIG. 2D schematically illustrates a schematic diagram of a window comparison subcircuit, in accordance with an embodiment of the present disclosure, and Fig. 3 schematically illustrates a flow chart of a data transmission method according to an embodiment of the present disclosure. Detailed Description Exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, which include various details of the embodiments of the present disclosure to facilitate understanding, and should be considered as merely exemplary. Accordingly, one of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness. The plurality of devices includes a master device and a plurality of slave devices, and the master device and the plurality of slave devices may enable data transfer between the master device and the plurality of slave devices based on a serial peripheral interface protocol. The serial extranet device interface is a high-speed, full duplex and synchronous communication bus. Before data transmission between a master device and a plurality of slave devices is achieved, a comm