CN-115980552-B - Chip testing system and method

CN115980552BCN 115980552 BCN115980552 BCN 115980552BCN-115980552-B

Abstract

The application discloses a chip test system, which relates to the field of chip detection and comprises an upper computer, a programmable power supply, a mounting test board, a ZYNQ main control chip, a chip to be tested, a power chip module and a communication serial port module, wherein the ZYNQ main control chip and the chip to be tested are connected through a first bus and a second bus, the ZYNQ main control chip is connected with the upper computer through the communication serial port module, the power chip module is connected with the upper computer through the programmable power supply and is respectively connected with the ZYNQ main control chip and the chip to be tested, and the upper computer is used for sending a test instruction to the ZYNQ main control chip through the communication serial port module, and controlling the system to enter a DFT mode or a mounting mode to test the chip to be tested. The system integrates the functions of an ATE test board and a packaging test board by utilizing the parallel capability of the PL/FPGA and the packaging function of the PS/ARM in the ZYNQ chip, the test process does not need repeated loading, the test period is reduced, and the test efficiency is greatly improved.

Inventors

Request for anonymity

Assignees

深存科技(无锡)有限公司

Dates

Publication Date: 20260508
Application Date: 20230118

Claims (7)

1. The chip test system is characterized by comprising an upper computer, a programmable power supply, a mounting test board, a ZYNQ main control chip, a chip to be tested, a power chip module and a communication serial port module, wherein the ZYNQ main control chip is loaded on the mounting test board; The ZYNQ master control chip and the chip to be tested are connected with each other through a first bus and a second bus, and the ZYNQ master control chip is connected with the upper computer through the communication serial port module in a communication way; the power chip module is connected with the upper computer through the programmable power supply, and is respectively connected with the ZYNQ main control chip and the chip to be tested and used for supplying power to the system; The upper computer is used for sending DFT instructions or mounting instructions to the ZYNQ main control chip through the communication serial port module, the control system enters a scanning chain DFT mode or a mounting mode and tests the chip to be tested, in the DFT mode, the ZYNQ main control chip initiates scanning of a plurality of circuits in the chip to be tested in parallel through the parallel function of the PL/FPGA, in the mounting function mode, the ZYNQ main control chip performs mounting function test on the chip to be tested through the PS/ARM and the mounting function test program running in the chip to be tested, the first bus is used for data interaction in the DFT mode, and the second bus is used for data interaction in the mounting mode.
2. The chip test system according to claim 1, wherein the mounting test board further includes a DDR memory, a first flash memory, a second flash memory, and two reset circuit modules; the DDR memory and the first flash memory are respectively connected with the ZYNQ master control chip, the second flash memory and the chip to be tested are respectively connected with a reset circuit module for initializing the chip; The first flash memory stores programs in a DFT mode and a mounting mode, and the second flash memory stores programs to be operated by the chip to be tested in the mounting mode.
3. The chip test system according to claim 2, wherein the ZYNQ main control chip is further connected with a first JTAG interface, and the chip to be tested is further connected with a second JTAG interface, which are respectively used for burning test programs into the corresponding flash memories of the respective chips.
4. The chip test system according to claim 1, wherein the power chip module is further connected with a current limiting and overvoltage protection module, and the programmable power supply is connected with the power chip module based on a GPIB interface.
5. The chip test system according to claim 2, wherein when the system enters a DFT mode, the ZYNQ master chip carries a DFT scan chain program in the first flash memory to the DDR memory connected thereto for operation by reading the DFT scan chain program, and performs DFT scan on the chip to be tested through the first bus; The ZYNQ main control chip applies test excitation signals under each functional module to an output pin of the chip to be tested and receives feedback signals output by the chip to be tested; And the ZYNQ main control chip collects and compares the test excitation signal with the feedback signal, counts the error times and the error rate, reports the statistical result to the upper computer for data processing and displaying test data.
6. The chip test system according to claim 2, wherein when the system enters a real-world mode, the ZYNQ master chip carries the real-world test program in the first flash memory to the DDR memory connected with the ZYNQ master chip for operation by reading the real-world test program, and controls the chip to be tested to operate the real-world test program through the second bus; The ZYNQ main control chip performs functional interaction with the chip to be tested, and whether the chip to be tested is normal in various functions is tested; and the ZYNQ main control chip reports the test results of various functions to the upper computer for display and data processing.
7. The chip test system according to claim 5 or 6, wherein after the host computer sends a DFT instruction or a mounting instruction to the ZYNQ main control chip, the current limiting and overvoltage protection module detects and displays the system voltage and current, and when the system voltage or current exceeds a normal value, the programmable power supply is turned off and the test is ended.

Description

Chip testing system and method Technical Field The embodiment of the application relates to the field of chip detection, in particular to a chip testing system and method. Background In the chip production process flow, after the chip production is finished, the detection work before leaving the factory is needed to be carried out on the produced chip through a detection department, so that each module and function of the chip can be ensured to normally operate. The test content at least comprises interrupt, serial port, reset, GPIO, memory function and the like. The chip detection at the current stage is mainly divided into two parts, namely 1, function and performance testing is carried out on an ATE machine table by utilizing an ATE test board, and 2, the mounting function is carried out on a mounting function testing system. That is, at least two sets of test systems are required to be prepared for completing a finished chip test flow, which results in that the chip needs to be loaded and tested back and forth on two machine stations for completing the whole test flow, the process of starting and stopping during intermediate transfer loading prolongs the whole test period, the process is complicated, and the development difficulty and the period of test programs required by ATE machine stations are large, so that the test of a large number of chips is not facilitated. Disclosure of Invention The embodiment of the application provides a chip testing system, which solves the problems of long chip testing period and complicated detection. The system comprises an upper computer, a programmable power supply, a mounting test board, a ZYNQ main control chip, a chip to be tested, a power chip module and a communication serial port module, wherein the ZYNQ main control chip is loaded on the mounting test board; The ZYNQ master control chip and the chip to be tested are connected with each other through a first bus and a second bus, and the ZYNQ master control chip is connected with the upper computer through the communication serial port module in a communication way; the power chip module is connected with the upper computer through the programmable power supply, and is respectively connected with the ZYNQ main control chip and the chip to be tested and used for supplying power to the system; The upper computer is used for sending a test instruction to the ZYNQ main control chip through the communication serial port module, controlling the system to enter a scanning chain DFT mode or a mounting mode, and testing the chip to be tested; the first bus is used for data interaction in the DFT mode, and the second bus is used for data interaction in the packaging mode. Specifically, the mounting test board is also provided with a DDR memory, a first flash memory, a second flash memory and two reset circuit modules; the DDR memory and the first flash memory are respectively connected with the ZYNQ master control chip, the second flash memory and the chip to be tested are respectively connected with a reset circuit module for initializing the chip; The first flash memory stores programs in a DFT mode and a mounting mode, and the second flash memory stores programs to be operated by the chip to be tested in the mounting mode. Specifically, the ZYNQ main control chip is also connected with a first JTAG interface, and the chip to be tested is also connected with a second JTAG interface, which are respectively used for burning test programs into the corresponding flash memories of the respective chips. Specifically, the power chip module is also connected with a current limiting and overvoltage protection module, and the programmable power supply is connected with the power chip module based on a GPIB interface. Specifically, a system test mode sends DFT instructions and mounting instructions through the upper computer, the ZYNQ main control chip initiates scanning of a plurality of circuits in the chip to be tested in parallel through the parallel function of the PL/FPGA in the ZYNQ main control chip in the DFT mode, and the ZYNQ main control chip performs mounting function test on the chip to be tested through the PS/ARM in the ZYNQ main control chip and the mounting function test program running in the chip to be tested in the mounting function mode. Specifically, when the system enters a DFT mode, the ZYNQ main control chip carries the DFT scanning chain program in the first flash memory to the DDR memory connected with the ZYNQ main control chip for operation by reading the DFT scanning chain program, and performs DFT scanning on the chip to be tested through the first bus; The ZYNQ main control chip applies test excitation signals under each functional module to an output pin of the chip to be tested and receives feedback signals output by the chip to be tested; And the ZYNQ main control chip collects and compares the test excitation signal with the feedback signal, counts the error times and the error rate, reports