CN-115985378-B - Method and device for self-testing configuration memory in FPGA

Abstract

The invention provides a method and a device for self-testing a configuration memory in an FPGA. The method comprises the steps of locking the input of all multiplexers MUXs in the FPGA to be at the same level, writing a first preset vector into the configuration memory based on a shift chain in a parallel mode, then reading the configuration memory based on the shift chain to obtain first read data, writing a second preset vector into the configuration memory based on the shift chain when the first read data is consistent with the first preset vector, reading the configuration memory based on the shift chain to obtain second read data, and judging that the configuration memory passes a test when the second read data is consistent with the second preset vector. Therefore, parallelization of the test path is realized, the test speed is increased, the MUX input end is fixed to be the same level, and the short circuit problem is avoided. And (3) performing automatic traversal test on the distributed memory without limiting the read-write vector, thereby completing the test work.

Inventors

• WANG PANFENG
• WANG HAILI

Assignees

• 京微齐力(北京)科技股份有限公司

Dates

Publication Date

20260508

Application Date

20221222

Claims (10)

1. 1. A method for configuration memory self-test in an FPGA, the method comprising: when the built-in self-test BIST signal of the FPGA is effective, locking the input ends of all the single-heat coding multiplexers MUXs in the FPGA to be at the same level; writing a first preset vector into the configuration memory based on a shift chain in a parallel form; reading the configuration memory based on the shift chain to obtain first read data; Writing a second preset vector into the configuration memory based on the shift chain when the first read data and the first preset vector are consistent; Reading the configuration memory based on the shift chain to obtain second read data; And when the second read data is consistent with a second preset vector, judging that the configuration memory passes the test.
2. 2. The method according to claim 1, wherein the method further comprises: And when the first readout data and the first preset vector are inconsistent, judging that the configuration memory fails the test.
3. 3. The method according to claim 1, wherein the method further comprises: and when the second read data is inconsistent with a second preset vector, judging that the configuration memory fails the test.
4. 4. The method of claim 1, wherein locking the inputs of all of the multiplexers MUX in the FPGA to the same level comprises: The signals input to the multiplexer MUX are set to either high or low.
5. 5. The method of claim 1, wherein the parallel-based shift chain is one of a 4-bit shift chain, an 8-bit shift chain, or a 16-bit shift chain.
6. 6. The method of claim 1, wherein the vector elements in the first predetermined vector are all 1 and the vector elements in the second predetermined vector are all 0.
7. 7. An apparatus for configuration memory self-test in an FPGA, the apparatus comprising: The input locking module is used for locking the input ends of all the single-hot coding multiplexers MUXs in the FPGA to be at the same level when the BIST signals of the FPGA are valid; The first writing module is used for writing a first preset vector into the configuration memory based on a shift chain in a parallel form; the first reading module is used for reading the configuration memory based on the shift chain to obtain first read data; a second writing module, configured to write a second preset vector into the configuration memory based on the shift chain when the first read data and the first preset vector are consistent; The second reading module is used for reading the configuration memory based on the shift chain to obtain second read data; and the test judging module is used for judging that the configuration memory passes the test when the second read data is consistent with a second preset vector.
8. 8. The apparatus of claim 7, wherein the test decision module is further to: And when the first readout data and the first preset vector are inconsistent, judging that the configuration memory fails the test.
9. 9. The apparatus of claim 7, wherein the test decision module is further to: and when the second read data is inconsistent with a second preset vector, judging that the configuration memory fails the test.
10. 10. The apparatus of claim 7, wherein the parallel-based form of shift chain is one of a 4-bit shift chain, an 8-bit shift chain, or a 16-bit shift chain.

Description

Method and device for self-testing configuration memory in FPGA Technical Field One or more embodiments of the present disclosure relate to the field of electronic technology, and in particular, to a method and apparatus for self-testing a configuration memory in an FPGA. Background At present, a field programmable gate array (FieldProgrammableGateArray, abbreviated as FPGA) is used as a semi-custom circuit in the field of application specific integrated circuits, which not only solves the defect of custom circuits, but also overcomes the defect of limited gate circuits of the original programmable devices. However, each sub-module in the FPGA currently has a corresponding Test circuit, such as a programmable logic block (Configurable LogicBlocks, CLB for short), a digital signal processor (DigitalSignalProcess, DSP for short), an embedded system (EmbeddedSystem, EMB for short), etc., but lacks a built-in self-Test circuit (Built-InSelf-Test, BIST for short) for a distributed configuration memory (ConfigurationMemory, cfgmem). The reason is that the FPGA contains many single-hot-coded multiplexers (OneHotMultiplexer, oneHotMUX) and the general BIST approach can cause chip shorting. The existing method has long test time and high test cost because the cost increases in geometric multiples along with the increase of the scale. Disclosure of Invention The invention describes a method and a device for self-testing a configuration memory in an FPGA, which can solve the technical problems. According to a first aspect, a method of configuration memory self-test in an FPGA is provided. The method comprises the following steps: When the built-in self-test BIST signals of the FPGA are valid, the inputs of all multiplexers MUXs in the FPGA are locked to be at the same level, a first preset vector is written into the configuration memory based on a shift chain in a parallel mode, the configuration memory is read based on the shift chain to obtain first read data, when the first read data is consistent with the first preset vector, a second preset vector is written into the configuration memory based on the shift chain, the configuration memory is read based on the shift chain to obtain second read data, and when the second read data is consistent with the second preset vector, the configuration memory is judged to pass the test. In some embodiments, before the built-in self-test BIST signal of the FPGA is valid, the method further includes configuring the configuration memory into an actual use mode, initializing a configuration register. In some embodiments, it is determined that the configuration memory fails the test when the first sensed data and the first predetermined vector are inconsistent. In some embodiments, it is determined that the configuration memory fails the test when the second readouts and second preset vectors are inconsistent. In some embodiments, the locking the inputs of all of the multiplexer MUXs in the FPGA to the same level includes setting the signal input to the multiplexer MUX to either a high level or a low level. In some embodiments, the parallel-based form of shift chain is one of a 4-bit shift chain, an 8-bit shift chain, or a 16-bit shift chain. In some embodiments, the vector elements in the first predetermined vector are all 1, and the vector elements in the second predetermined vector are all 0. According to a second aspect, an apparatus for configuration memory self-test in an FPGA is provided. The device comprises: The device comprises a configuration memory, an input locking module, a first writing module, a first reading module, a second writing module and a test judging module, wherein the input locking module is used for locking the inputs of all multiplexers MUXs in the FPGA to be at the same level when the BIST signals of the FPGA are valid, the first writing module is used for writing a first preset vector into the configuration memory based on a shift chain in a parallel mode, the first reading module is used for reading the configuration memory based on the shift chain to obtain first read data, the second writing module is used for writing a second preset vector into the configuration memory based on the shift chain when the first read data and the first preset vector are consistent, the second reading module is used for reading the configuration memory based on the shift chain to obtain second read data, and the test judging module is used for judging that the configuration memory passes a test when the second read data and the second preset vector are consistent. In some embodiments, the test determination module is further configured to determine that the configuration memory fails the test when the first read data and the first preset vector do not match. In some embodiments, the test determination module is further configured to determine that the configuration memory fails the test when the second sensed data and a second predetermined vector are inconsistent. In