CN-115985793-B - Semiconductor performance test method and system

CN115985793BCN 115985793 BCN115985793 BCN 115985793BCN-115985793-B

Abstract

The invention relates to a semiconductor performance test method and system, belongs to the technical field of semiconductors, and solves the problem that defects in unordered dielectric layers and defects at interfaces influence the transport performance of carriers in a semiconductor active layer. The method comprises the steps of preparing a field effect transistor, measuring drain current corresponding to grid voltage along with continuous change of the grid voltage in a test voltage range, drawing a transfer characteristic curve according to the grid voltage value and the corresponding drain current value in the test voltage range, connecting a drain electrode of the field effect transistor to a positive power supply voltage, connecting a source electrode to the ground and connecting the grid electrode to the grid voltage which is changed in the test voltage range, and obtaining intrinsic transport performance of the semiconductor layer to be tested according to the transfer characteristic curve. The device structure with real semiconductor intrinsic transport performance is reflected by eliminating the influence of the defect of the insulating layer through the air (vacuum) insulating layer.

Inventors

WANG JIAWEI
ZHAO YING
BAI ZIHENG
LI LING
LU NIANDUAN

Assignees

中国科学院微电子研究所

Dates

Publication Date: 20260505
Application Date: 20211014

Claims (8)

1. A method for testing semiconductor performance, comprising: Preparing a field effect transistor, wherein the field effect transistor comprises an air insulating layer positioned between a semiconductor layer to be tested and a grid electrode, forming the semiconductor layer to be tested, a source electrode and a drain electrode above a substrate, and forming a side wall layer above the substrate except the source electrode and the drain electrode; Measuring a drain current corresponding to a gate voltage as the gate voltage continuously varies within a test voltage range, and drawing a transfer characteristic curve according to a gate voltage value and a corresponding drain current value within the test voltage range, wherein a drain of the field effect transistor is connected to a positive power supply voltage, a source is grounded, and a gate is connected to the gate voltage varying within the test voltage range, and Acquiring the intrinsic transport performance of the semiconductor layer to be tested according to the transfer characteristic curve, wherein the source comprises a source body, a source extension part and a source contact, the drain comprises a drain body, a drain extension part and a drain contact, and the side wall layer comprises a first side wall layer, a second side wall layer and a third side wall layer, wherein the source body is positioned above the semiconductor layer to be tested, the source extension part extends outwards from the middle part of the source body perpendicularly to the source body and is positioned above the substrate, and the source contact is positioned at the end part of the source extension part far away from the source body; The semiconductor device comprises a first side wall layer, a second side wall layer, a third side wall layer, a first side wall layer, a second side wall layer, a drain electrode extension and a grid electrode, wherein the first side wall layer is provided with a circular ring-shaped cross section and surrounds the semiconductor layer to be tested at 360 degrees, the second side wall layer comprises a plurality of rectangular cross sections and is located on one side of the first side wall layer, the source electrode extension is clamped between any two rectangular cross sections of the plurality of rectangular cross sections, the third side wall layer comprises a plurality of rectangular cross sections and is located on the other side of the first side wall layer, the drain electrode extension is clamped between any two rectangular cross sections of the plurality of rectangular cross sections, and the grid electrode is supported through the first side wall layer, the second side wall layer and the third side wall layer so as to generate an air insulating layer which is uniform in height and stable between the semiconductor layer to be tested and the grid electrode.
2. The method of claim 1, wherein the semiconductor layer to be tested comprises indium gallium zinc oxide, amorphous silicon, low temperature polysilicon, and disordered organic thin film.
3. The method of claim 2, wherein preparing a field effect transistor further comprises: Wherein a top surface of the semiconductor layer to be tested between the source electrode and the drain electrode is exposed; Wherein the height of the side wall layer is larger than the height of the semiconductor layer, the source electrode and the drain electrode, and And forming a grid electrode above the side wall layer so as to form the air insulating layer between the bottom surface of the grid electrode and the top surfaces of the source electrode, the drain electrode and the exposed top surface of the semiconductor layer to be tested.
4. The semiconductor performance testing method of claim 3, wherein forming the semiconductor layer to be tested, source and drain over a substrate further comprises: Evaporating a semiconductor material to be tested on the substrate by a magnetron sputtering method; patterning the semiconductor material to be tested through an ultraviolet lithography process and a wet etching process to form the semiconductor layer to be tested; Evaporating an electrode material layer over the substrate and the semiconductor layer by a photoresist coating process and an electron beam process, and The electrode material layer is patterned to form the source electrode and the drain electrode.
5. The semiconductor performance testing method of claim 3, wherein forming a gate over the sidewall layer further comprises: Cutting a heavily doped silicon wafer, and overlapping the cut heavily doped silicon wafer above the side wall layer to serve as the grid electrode, wherein the grid electrode covers the whole semiconductor layer to be tested, the side wall layer, the source electrode body, the source electrode extension part, the drain electrode body and the drain electrode extension part.
6. The method of testing semiconductor performance according to claim 2, wherein obtaining the intrinsic transport properties of the semiconductor layer to be tested from the transfer characteristic curve further comprises: obtaining the fitting slope of the linear region according to the transfer characteristic curve and The intrinsic mobility of the semiconductor layer is obtained based on the fitted slope of the linear region.
7. The semiconductor performance testing method according to claim 1, characterized by further comprising, before measuring the drain current corresponding to the gate voltage: fixing the field effect transistor on a sealed test bench; Selectively evacuating the sealed test bench with a vacuum pump; Adjusting the temperature of the test bench to 300K to obtain a normal temperature transfer characteristic curve of the semiconductor layer to be tested according to the measurement result, and And adjusting the temperature of the test bench to be different from 300K so as to obtain a temperature change transfer characteristic curve of the semiconductor layer to be tested according to the measurement result.
8. A semiconductor performance test system is characterized by comprising a field effect transistor and a semiconductor tester, wherein, The field effect transistor is placed in a test chamber of the semiconductor tester, and then a semiconductor layer to be tested in the field effect transistor is tested using the semiconductor performance test method according to any one of claims 1 to 7.

Description

Semiconductor performance test method and system Technical Field The present invention relates to the field of semiconductor technologies, and in particular, to a method and a system for testing performance of a semiconductor. Background Mobility, which is an important indicator for the transport performance of semiconductors, is defined as the drift velocity of electrons per unit field strength, and is an important charge transport parameter. There are many techniques for characterizing mobility, such as the time of flight method, space charge limited current method, field Effect Transistor (FET) method. The field effect transistor method is widely used as a method for preparing a semiconductor material of a field effect transistor. In general, three-terminal devices (gate, source, drain) are manufactured, carriers are injected from a grounded source electrode under the induction of gate voltage, drift current is formed under the action of voltage between the source and the drain, and the carriers are received by the drain. For amorphous semiconductors, the semiconductor energy density exhibits a gaussian or exponential distribution, with the band edge having a slope, i.e., with a tail state, by which is meant that the edges of the conduction and valence bands in the semiconductor are not abrupt. In actual semiconductors, however, the ideal lattice periodicity is destroyed by the formation of defects, doping, etc., and some localized states are formed. The energy density distribution corresponds to a continuous energy state distribution in a forbidden band region near the bottom of the conduction band or the top of the valence band, and is in the form of a tail, namely, a band tail, in the forbidden band. Carriers in the tail state are not well extended and therefore tend to cause degradation of the electrical properties of the semiconductor. When the semiconductor band tail state is very small, namely the slope is relatively large, the carrier can jump into the energy band for transportation, the mobility is high, when the band tail state is very large, the fermi level is positioned in the band tail state, and the mobility of the device is influenced by localized carriers in the band tail state and can be greatly reduced. The vertical structure of a conventional field effect transistor comprises a metal gate, a dielectric layer (insulating layer) and a semiconductor active layer. Many defects exist in the disordered dielectric layer, so that the semiconductor band tail state becomes large, and the transport of carriers in the semiconductor active layer is influenced. In addition, interface defects and the like of the dielectric layer and the semiconductor layer can introduce more disorder into the semiconductor, so that the transport performance is deteriorated. Therefore, the FET characterization method is influenced by the dielectric layer, and the intrinsic transport characteristic of the semiconductor layer is difficult to reflect truly, and the research on the intrinsic transport performance of the semiconductor layer is a key factor for improving the field effect semiconductor device. Better interface performance can be obtained by a method for improving the lattice matching of the insulating layer and the semiconductor layer, but no completely matched insulating layer material exists for materials such as amorphous oxide, organic semiconductor and the like, so that the influence of interface defects of a dielectric layer and the semiconductor layer is eliminated for field effect transistors of the materials such as amorphous oxide, organic semiconductor and the like, and the method is a technical problem to be solved in the research of the transport performance of an intrinsic semiconductor. Disclosure of Invention In view of the above analysis, the embodiments of the present invention aim to provide a method and a system for testing semiconductor performance, which are used for solving the problem that the existing unordered defects in the dielectric layer and the interface defects between the dielectric layer and the semiconductor layer affect the transport performance of carriers in the semiconductor active layer. On one hand, the embodiment of the invention provides a semiconductor performance testing method, which comprises the steps of preparing a field effect transistor, measuring drain current corresponding to grid voltage along with continuous change of the grid voltage in a testing voltage range, drawing a transfer characteristic curve according to the grid voltage value and the corresponding drain current value in the testing voltage range, wherein the drain electrode of the field effect transistor is connected with a positive power supply voltage, the source electrode of the field effect transistor is grounded, and the grid electrode of the field effect transistor is connected with the grid voltage which is changed in the testing voltage range, and acquiring the intrinsic transport perf