CN-115985945-B - Semiconductor device and manufacturing method thereof

CN115985945BCN 115985945 BCN115985945 BCN 115985945BCN-115985945-B

Abstract

The application provides a semiconductor device and a manufacturing method thereof, wherein the semiconductor device comprises a substrate, a source electrode, a drain electrode, a grid electrode and a channel structure, wherein the source electrode, the drain electrode, the grid electrode and the channel structure are arranged on one side of the substrate, the channel structure comprises a lamination formed by a plurality of nano sheets, the grid electrode surrounds the nano sheets, the nano sheets comprise edge areas and central areas, the thickness of the nano sheets in the central areas is smaller than that of the nano sheets in the edge areas in the direction perpendicular to the plane of the substrate, that is, the nano sheets form a structure with a thin middle edge, the thickness and the volume of other structures between adjacent nano sheets are reduced, the parasitic resistance of the semiconductor device is reduced, in addition, the thickness of the nano sheets in the area close to the source electrode or the drain electrode is larger, the contact area of the source electrode and the drain electrode is larger, the heat generated by the channel structure can be conducted to the source electrode and the drain electrode through the increased contact area, the heat dissipation efficiency is accelerated, the heat dissipation effect is enhanced, and the performance of the finally manufactured semiconductor device is improved.

Inventors

YIN HUAXIANG
ZHAO PENG
WU ZHENHUA
ZHANG ZHAOHAO

Assignees

中国科学院微电子研究所

Dates

Publication Date: 20260512
Application Date: 20230223

Claims (6)

1. A semiconductor device, the semiconductor device comprising: A substrate; the source electrode, the drain electrode and the channel structure are arranged on one side of the substrate, the channel structure is positioned between the source electrode and the drain electrode, and the channel structure comprises a lamination formed by a plurality of nano sheets; The nano-sheet comprises an edge area and a central area, wherein the edge area is an area of the nano-sheet close to the source electrode or the drain electrode, the central area is an area of the nano-sheet far away from the source electrode or the drain electrode, and the thickness of the nano-sheet in the central area is smaller than that of the nano-sheet in the edge area in the direction perpendicular to the plane of the substrate; a gate surrounding the nanoplatelets; an inner side wall is arranged between the adjacent nano sheets, and the thickness of one side of the inner side wall, which is close to the source electrode or the drain electrode, is smaller than the thickness of the inner side wall, which is far away from the source electrode or the drain electrode, in the direction perpendicular to the plane of the substrate; the interface of the inner side wall and the nanosheets in contact is a cambered surface.
2. The semiconductor device of claim 1, wherein the thickness of the nanoplatelets increases gradually along a direction of a central region of the nanoplatelets toward an edge region of the nanoplatelets.
3. The semiconductor device of claim 2, wherein the thickness of the inner sidewall gradually decreases along a direction of a central region of the nanoplatelets toward an edge region of the nanoplatelets.
4. A semiconductor device according to any one of claims 1-3, wherein the material of the inner sidewall is one or more of silicon oxide, silicon nitride, aluminum oxide, silicon oxynitride, low-k material and air.
5. A method of manufacturing a semiconductor device, the method comprising: Providing a substrate, and forming a plurality of laminated structures formed by alternately laminating a first semiconductor layer and a second semiconductor layer on one side of the substrate; etching the laminated structure to form a source electrode region and a drain electrode region, wherein a channel region is arranged between the source electrode region and the drain electrode region; selectively etching the first semiconductor layer in the channel region along a first direction, wherein the thickness of the second semiconductor layer in the central region is smaller than that of the second semiconductor layer in the edge region in a direction perpendicular to the plane of the substrate; the second semiconductor layer comprises an edge area and a central area, wherein the edge area is an area of the second semiconductor layer close to the source electrode area or the drain electrode area, and the central area is an area of the second semiconductor layer far away from the source electrode area or the drain electrode area; forming a source and a drain in the source region and the drain region, respectively; Replacing the first semiconductor layer with a grid, wherein the grid surrounds the second semiconductor layer, and a channel structure is formed by a lamination formed by a plurality of second semiconductor layers; the selectively etching the first semiconductor layer along a first direction at the channel region includes: Etching the first semiconductor layer along a first direction by utilizing a selective embedded Cavity etching process; before the source and drain regions are formed respectively, the method further comprises: forming an inner side wall in the channel region, wherein the inner side wall is positioned between the adjacent second semiconductor layers; in the direction perpendicular to the plane of the substrate, the thickness of one side of the inner side wall, which is close to the source electrode or the drain electrode, is smaller than the thickness of the inner side wall, which is far away from the source electrode or the drain electrode; And the interface of the inner side wall and the second semiconductor layer, which is contacted, is an arc surface.
6. The method of manufacturing of claim 5, wherein the replacing the first semiconductor layer with a gate electrode comprises: Removing the first semiconductor layer, and forming a plurality of gaps to be filled between the second semiconductor layers; And filling the grid electrode in a plurality of gaps to be filled.

Description

Semiconductor device and manufacturing method thereof Technical Field The present invention relates to the field of semiconductors, and more particularly, to a semiconductor device and a method of manufacturing the same. Background With the development of semiconductor technology, the feature size of integrated circuits continues to shrink, and the conventional tri-gate or dual-gate Fin Field effect transistor (Fin Field-Effect Transistor, finFET) is limited by the shrinking of gate control failure and leakage degradation at nodes below 3 nanometers (nm), and because the nanosheet ring gate transistor (Nanosheet Gate-all-round Field-Effect Transistor, nanosheet GAAFET) breaks through the limitation of the 3nm node, the technology is widely focused and studied. Nanosheet GAAFET is a novel device having a gate-all-around structure and stacked horizontal nanoplates (Nanosheet, NS) as conductive channels. In the aspect of gate control, the gate-surrounding structure has better gate control capability than the FinFET device structure, short channel effect of the device can be effectively inhibited, nanosheet GAAFET has inversion carriers of 'body inversion', and in the aspect of current driving, the increase of effective gate width and the design of nano-sheet stacking in the vertical direction can also obviously enhance the current driving performance of the device. However, at present Nanosheet GAAFET, because of the isolation between the stacked nano-sheet channel and the source drain, the parasitic resistance from the channel to the source drain is larger, the heat dissipation performance is poorer, the power consumption of the device is increased, and the overall performance is reduced. Disclosure of Invention In view of the above, an object of the present application is to provide a semiconductor device and a method for manufacturing the same, which can reduce parasitic resistance of the semiconductor device, enhance heat dissipation effect, and improve performance of the semiconductor device finally manufactured. An embodiment of the present application provides a semiconductor device including: A substrate; the source electrode, the drain electrode and the channel structure are arranged on one side of the substrate, the channel structure is positioned between the source electrode and the drain electrode, and the channel structure comprises a lamination formed by a plurality of nano sheets; The nano-sheet comprises an edge area and a central area, wherein the edge area is an area of the nano-sheet close to the source electrode or the drain electrode, the central area is an area of the nano-sheet far away from the source electrode or the drain electrode, and the thickness of the nano-sheet in the central area is smaller than that of the nano-sheet in the edge area in the direction perpendicular to the plane of the substrate; A gate surrounding the nanoplatelets. Optionally, the thickness of the nanoplatelets increases gradually along a direction of a central region of the nanoplatelets toward an edge region of the nanoplatelets. Optionally, an inner side wall is disposed between adjacent nano sheets, and in a direction perpendicular to a plane where the substrate is located, a thickness of a side of the inner side wall, which is close to the source electrode or the drain electrode, is smaller than a thickness of the inner side wall, which is far away from the source electrode or the drain electrode. Optionally, the thickness of the inner side wall gradually decreases along a direction of the central region of the nano-sheet toward the edge region of the nano-sheet. Optionally, the contact interface between the inner side wall and the nano sheet is an arc surface. Optionally, the material of the inner side wall is one or more of silicon oxide, silicon nitride, aluminum oxide, silicon oxynitride, silicon oxycarbide, boron nitride, low-k material and air. The embodiment of the application provides a manufacturing method of a semiconductor device, which comprises the following steps: Providing a substrate, and forming a plurality of laminated structures formed by alternately laminating a first semiconductor layer and a second semiconductor layer on one side of the substrate; etching the laminated structure to form a source electrode region and a drain electrode region, wherein a channel region is arranged between the source electrode region and the drain electrode region; selectively etching the first semiconductor layer in the channel region along a first direction, wherein the thickness of the second semiconductor layer in the central region is smaller than that of the second semiconductor layer in the edge region in a direction perpendicular to the plane of the substrate; the second semiconductor layer comprises an edge area and a central area, wherein the edge area is an area of the second semiconductor layer close to the source electrode area or the drain electrode area, and the central area is an area of