CN-116015217-B - Broadband low-power-consumption transconductance operational amplifier with enhanced slew rate

CN116015217BCN 116015217 BCN116015217 BCN 116015217BCN-116015217-B

Abstract

The invention discloses a broadband low-power-consumption transconductance operational amplifier with enhanced slew rate, which comprises an improved cyclic folding transconductance operational amplifier and a slew rate enhancement circuit, wherein the slew rate enhancement circuit can remarkably improve positive and negative slew rates during large-signal operation of the amplifier, and a transistor of the slew rate enhancement circuit works in a subthreshold region during small-signal operation of the amplifier, so that current is hardly consumed, and the unit gain bandwidth and slew rate of the amplifier can be improved under the condition of keeping low power consumption, thereby improving the working speed and the output current capability of the operational amplifier. The embodiment of the invention improves the working speed of the high-performance switched capacitor circuit, reduces the power consumption, is easy to popularize and use, and can be widely applied to the technical field of operational amplifiers.

Inventors

SU TAO
HU BINGXIANG
WANG ZIXIN
Mou Bingrui
LIANG YAN
ZHU WENLI

Assignees

中山大学

Dates

Publication Date: 20260505
Application Date: 20230110

Claims (8)

1. The broadband low-power consumption transconductance operational amplifier is characterized by comprising an improved circulating folding transconductance operational amplifier and a slew rate enhancement circuit, wherein the improved circulating folding transconductance operational amplifier comprises a third PMOS tube, an eighth PMOS tube, a first NMOS tube, a fourth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a fifth PMOS tube, a thirteenth PMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube and a fifteenth NMOS tube, and the slew rate enhancement circuit comprises a first PMOS tube, a second PMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a sixth PMOS tube, a seventh PMOS tube, a sixteenth NMOS tube, a seventeenth NMOS tube and an eighteenth NMOS tube, wherein: The first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube, the sixth PMOS tube and the seventh PMOS tube are all connected to an analog positive power supply, the grid electrodes of the first PMOS tube and the second PMOS tube are all connected with the drain electrode of the seventh NMOS tube, the drain electrode of the second PMOS tube is connected with a differential output negative end, the drain electrode of the seventeenth NMOS tube, the drain electrode of the eighth PMOS tube and the drain electrode of the first NMOS tube, the grid electrode of the third PMOS tube is connected with a common mode feedback voltage, the drain electrode of the third PMOS tube is connected with the source electrode of the eighth PMOS tube, the grid electrode of the eighth PMOS tube is connected with a P-type first bias voltage, the drain electrode of the fourth PMOS tube is connected with the drain electrode of the ninth PMOS tube, the tenth PMOS tube, the eleventh PMOS tube and the source electrode of the twelfth PMOS tube are connected, the grid electrode of the fourth PMOS tube is connected with a P-type second bias voltage, the grid electrode of the fifth PMOS tube is connected with the common mode feedback voltage, the drain electrode of the fifth PMOS tube is connected to the source electrode of the thirteenth PMOS tube, the grid electrodes of the sixth PMOS tube and the seventh PMOS tube are connected with the drain electrode of the eighteenth NMOS tube, the drain electrode of the sixth PMOS tube is connected with the differential output positive end, the drain electrode of the eighth NMOS tube, the drain electrode of the thirteenth PMOS tube and the drain electrode of the second NMOS tube, the source electrode of the first NMOS tube is connected with the drain electrode of the ninth NMOS tube, The drain electrode of the tenth NMOS tube, the drain electrode of the ninth PMOS tube, the grid electrode of the seventh NMOS tube, the grid electrode of the eighth NMOS tube and the grid electrode of the ninth NMOS tube are connected, the grid electrode of the first NMOS tube is connected with a first N-type bias voltage, the grid electrode of the ninth PMOS tube and the grid electrode of the tenth PMOS tube are connected with a differential input positive end, the drain electrode of the tenth PMOS tube is connected with the drain electrode of the fifth NMOS tube, the drain electrode of the sixth NMOS tube, the grid electrode of the fourteenth NMOS tube and the grid electrode of the fifteenth NMOS tube, the drain electrode of the eleventh PMOS tube is connected with the drain electrode of the third NMOS tube, The drain electrode of the fourth NMOS tube, the gate electrode of the tenth NMOS tube and the gate electrode of the eleventh NMOS tube are connected, the gate electrode of the eleventh PMOS tube and the gate electrode of the twelfth PMOS tube are connected with a differential input negative terminal, the gate electrode of the thirteenth PMOS tube is connected with the P-type first bias voltage, the source electrode of the second NMOS tube is connected with the drain electrode of the fifteenth NMOS tube, the drain electrode of the sixteenth NMOS tube, the drain electrode of the twelfth PMOS tube, the gate electrode of the sixteenth NMOS tube, the gate electrode of the seventeenth NMOS tube and the gate electrode of the eighteenth NMOS tube, the gate electrode of the second NMOS tube is connected with the first N-type bias voltage, the source electrode of the third NMOS tube is connected with the drain electrode of the eleventh NMOS tube, the source electrode of the fourth NMOS tube is connected with the drain electrode of the twelfth NMOS tube, the source electrode of the fifth NMOS tube is connected with the drain electrode of the thirteenth NMOS tube, the source electrode of the sixth NMOS tube is connected with the drain electrode of the fourteenth NMOS tube, the third NMOS tube is connected with the drain electrode of the thirteenth NMOS tube, The gates of the fourth NMOS tube, the fifth NMOS tube and the sixth NMOS tube are all connected with the first N-type bias voltage, the gates of the twelfth NMOS tube and the thirteenth NMOS tube are all connected with the second N-type bias voltage, and the sources of the seventh NMOS tube, the eighth NMOS tube, the ninth NMOS tube, the tenth NMOS tube, the eleventh NMOS tube, the twelfth NMOS tube, the thirteenth NMOS tube, the fourteenth NMOS tube, the fifteenth NMOS tube, the sixteenth NMOS tube, the seventeenth NMOS tube and the eighteenth NMOS tube are all connected with the analog ground.
2. The broadband low-power consumption operational transconductance amplifier with enhanced slew rate according to claim 1, wherein the substrates of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, the twelfth NMOS transistor, the thirteenth NMOS transistor, the fourteenth NMOS transistor, the fifteenth NMOS transistor, the sixteenth NMOS transistor, the seventeenth NMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, the tenth PMOS transistor, the eleventh PMOS transistor, and the thirteenth NMOS transistor are all connected to the analog ground.
3. The broadband low-power consumption operational transconductance amplifier with increased slew rate of claim 2, wherein the potential of the analog ground is 0V and the potential of the analog positive power supply is 3.3V.
4. The broadband low-power consumption transconductance operational amplifier with enhanced slew rate as set forth in claim 1, wherein the transistors of the ninth PMOS transistor, the tenth PMOS transistor, the eleventh PMOS transistor and the twelfth PMOS transistor have the same size, and the transistors of the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor and the sixth NMOS transistor have the same size.
5. The broadband low-power consumption operational transconductance amplifier of claim 1, wherein the ratio of the transistor sizes of the ninth NMOS transistor, the eighth NMOS transistor and the seventh NMOS transistor is 1:m:n, the ratio of the transistor sizes of the sixteenth NMOS transistor, the seventeenth NMOS transistor and the eighteenth NMOS transistor is 1:m:n, and n=m+2.5, and the transistor sizes of the ninth NMOS transistor and the sixteenth NMOS transistor are the same.
6. The broadband low-power consumption transconductance operational amplifier with enhanced slew rate as set forth in claim 1, wherein the transistors of the first PMOS transistor, the second PMOS transistor, the sixth PMOS transistor and the seventh PMOS transistor are the same size.
7. The broadband low-power consumption transconductance operational amplifier with increased slew rate as set forth in claim 1, wherein the ratio of the transistor sizes of the tenth NMOS transistor, the eleventh NMOS transistor and the twelfth NMOS transistor is 6:1:1, the ratio of the transistor sizes of the fifteenth NMOS transistor, the fourteenth NMOS transistor and the thirteenth NMOS transistor is 6:1:1, and the transistor sizes of the twelfth NMOS transistor and the fifteenth NMOS transistor are the same.
8. A slew rate enhanced wideband low power consumption transconductance operational amplifier as claimed in any one of claims 1-7, wherein the common mode feedback voltage is generated by a switched capacitor common mode feedback circuit.

Description

Broadband low-power-consumption transconductance operational amplifier with enhanced slew rate Technical Field The invention relates to the technical field of operational amplifiers, in particular to a broadband low-power-consumption transconductance operational amplifier with enhanced slew rate. Background Transconductance operational amplifiers are one of the most important circuit units in analog circuits, and are widely used in analog circuits and mixed signal processing circuits, such as switched capacitors, analog-to-digital/digital-to-analog converters, and the like. Transconductance operational amplifiers generally determine the power consumption, accuracy, speed, etc. that can be achieved by high performance switched capacitor circuits. In the switched capacitor circuit, the load is usually a pure capacitive load, and the single-stage operational transconductance amplifier is superior to the multi-stage operational transconductance amplifier, so that the traditional folded transconductance amplifier is widely applied. The traditional folded transconductance amplifier has the defects of low current efficiency, low speed, high power consumption and the like, and can only be used for increasing the power consumption to improve the slew rate and the bandwidth, so that the design requirement of the current transconductance operational amplifier with high slew rate and large bandwidth is difficult to meet. In order to improve the current efficiency of the operational transconductance amplifier, a conventional folded cascode amplifier needs to be improved, and thus a cyclic folded transconductance operational amplifier is proposed, which uses a current multiplexing technology to improve the current efficiency of the operational amplifier. However, the existing cyclic folded transconductance operational amplifier has limited slew rate increase under the condition of limited power consumption, and the slew rates of positive and negative voltages are not equal, so that the achievable maximum output current is limited. Disclosure of Invention The present invention aims to solve at least one of the technical problems existing in the prior art to a certain extent. Therefore, an object of the embodiments of the present invention is to provide a broadband low-power-consumption transconductance operational amplifier with increased slew rate, which can improve the unity gain bandwidth and slew rate of the amplifier under the condition of keeping low power consumption, so as to improve the working speed and output current capability of the operational amplifier. In order to achieve the technical purpose, the technical scheme adopted by the embodiment of the invention comprises the following steps: The embodiment of the invention provides a broadband low-power consumption transconductance operational amplifier with enhanced slew rate, which comprises an improved cyclic folded transconductance operational amplifier and a slew rate enhancement circuit, wherein the improved cyclic folded transconductance operational amplifier comprises a third PMOS tube, an eighth PMOS tube, a first NMOS tube, a fourth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a fifth PMOS tube, a thirteenth PMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube and a fifteenth NMOS tube, and the slew rate enhancement circuit comprises a first PMOS tube, a second PMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a sixth PMOS tube, a seventh PMOS tube, a sixteenth NMOS tube, a seventeenth NMOS tube and an eighteenth NMOS tube, wherein: The first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube, the sixth PMOS tube and the seventh PMOS tube are all connected to an analog positive power supply, the grid electrodes of the first PMOS tube and the second PMOS tube are all connected with the drain electrode of the seventh NMOS tube, the drain electrode of the second PMOS tube is connected with a differential output negative end, the drain electrode of the seventeenth NMOS tube, the drain electrode of the eighth PMOS tube and the drain electrode of the first NMOS tube, the grid electrode of the third PMOS tube is connected with a common mode feedback voltage, the drain electrode of the third PMOS tube is connected with the source electrode of the eighth PMOS tube, the grid electrode of the eighth PMOS tube is connected with a P-type first bias voltage, the drain electrode of the fourth PMOS tube is connected with the drain electrode of the ninth PMOS tube, the tenth PMOS tube, the eleventh PMOS tube and the source electrode of the twelfth PMOS tube are connected, the grid electrode of the fourth PMOS tube is connected with a P-type second bias voltage, the grid electrode of the fif