CN-116015278-B - Circuit for accelerating long wiring setup time in chip

CN116015278BCN 116015278 BCN116015278 BCN 116015278BCN-116015278-B

Abstract

The invention discloses a circuit for accelerating the long wiring time in a chip, which belongs to the field of integrated circuits and comprises a front-stage BUFFER circuit, a rear-stage KEEPER circuit, a first MOS device and a second MOS device, wherein the BUFFER circuit and the KEEPER circuit are connected in series. The BUFFER circuit comprises a first inverter and a second inverter which are connected in series, the KEEPER circuit comprises a third inverter and a sixth inverter which are connected in series, and the output end of the second inverter is connected to the input end of the third inverter through a signal line. The source end of the second MOS device is connected with the GND signal, the drain end of the second MOS device is connected with the source end of the NMOS in the sixth inverter, the source end of the first MOS device is connected with the Vcc signal, the drain end of the first MOS device is connected with the source end of the PMOS in the sixth inverter, and the gate ends of the first MOS device and the second MOS device are respectively connected with the enabling signals which are independently supplied. According to the invention, by adding 2 switching MOS transistors, the conflict influence of the previous state on the signal line in the KEEPER circuit on the signal establishing time on the signal line is eliminated, the operation is simple and easy, and the layout area and the cost are saved.

Inventors

ZHANG BAOXIA
ZHU QI
XIAO PEILEI

Assignees

中国电子科技集团公司第五十八研究所

Dates

Publication Date: 20260512
Application Date: 20221226

Claims (3)

1. The circuit for accelerating the long wiring establishment time in the chip is characterized by comprising a front-stage BUFFER circuit, a rear-stage KEEPER circuit, a first MOS device and a second MOS device, wherein the BUFFER circuit and the KEEPER circuit are connected in series; The BUFFER circuit comprises a first inverter and a second inverter, wherein the INPUT end of the first inverter is connected with an INPUT signal INPUT, and the output end of the first inverter is connected with the INPUT end of the second inverter; the KEEPER circuit comprises a third inverter and a sixth inverter, wherein the output end of the third inverter is connected with the input end of the sixth inverter, and the output end of the third inverter is the output end of the whole circuit; The output end of the BUFFER circuit, namely the output end of the second inverter, is connected to the input end of the KEEPER circuit, namely the input end of the third inverter through a first signal line; The source electrode end of the first MOS device is connected with a Vcc signal, the drain electrode end of the first MOS device is connected with the source electrode end of a PMOS in the sixth inverter; the gate end of the second MOS device is connected with an enable signal, and the gate end of the first MOS device is connected with an enable_B signal; the first MOS device is a PMOS tube, and the second MOS device is an NMOS tube; The gate end of the second MOS device is connected with an enable signal, and the gate end of the first MOS device is connected with an enable_B signal; When the INPUT signal INPUT level is 1, the signal level is maintained to be 1 after passing through the BUFFER circuit and then passes through the first signal line, a large RC load needs time when the INPUT signal INPUT level is transmitted to the KEEPER circuit, before the voltage level on the first signal line rises to the threshold voltage Vth of the NMOS in the third inverter, the signal level on the second signal line is maintained to be 1, and then the INPUT signal INPUT level is fed back to the first signal line to be 0 through the sixth inverter, the first signal line needs to be pulled up to be higher than the Vth as soon as possible, the Vth is the threshold voltage of the NMOS in the third inverter, and the whole circuit can work normally; the source end of the second MOS device is connected with the ground GND, the drain end of the second MOS device is connected with the source end of the NMOS in the sixth inverter, the gate end of the second MOS device is set to be low level before the voltage level on the first signal line rises to the threshold voltage Vth of the NMOS in the third inverter, the feedback signal output of the sixth inverter is turned off, the influence of the signal level of the previous state on the feedback signal on the second signal line is shielded, when the voltage level on the first signal line rises to the threshold voltage Vth, the gate end of the second MOS device is set to be high level, at the moment, the signal level on the second signal line is 0, after passing through the sixth inverter, the voltage level fed back to the first signal line becomes 1 to accelerate the signal establishing time on the first signal line, otherwise, when the INPUT signal INPUT level is 0, after passing through the BUFFER circuit, the signal level is maintained to be 0, and then the first signal line passes through the first signal line, a large RC load causes the time to be required for being transmitted to the KEEPER circuit, before the voltage level on the first signal line is reduced from the previous state '1' to the threshold voltage Vth of the PMOS in the third inverter, the signal level on the second signal line is maintained to be '0', and then the signal level on the first signal line is output to be '1' through the sixth inverter, the first signal line is required to be reduced below the threshold voltage Vth as soon as possible, the whole circuit can work normally, the source end of the first MOS device is connected with the ground GND, the drain end of the first MOS device is connected with the source end of the PMOS in the sixth inverter, the gate end of the first MOS device is set to be high level, the feedback signal output of the sixth inverter is turned off, the influence of the signal level of the previous state on the feedback signal is shielded, when the voltage level on the first signal line is reduced to the threshold voltage Vth, the gate end of the first MOS device is set to be low level, and the signal level on the second signal line is set to be '1', after the voltage level on the second signal line is required to be reduced below the threshold voltage Vth through the sixth inverter, the voltage level on the first signal line is changed to be '0', the effect of accelerating the voltage level on the first signal line is achieved, and the time of the signal on the first signal line is accelerated; the first signal line is a signal line between the second inverter and the third inverter, and the second signal line is a signal line between the third inverter and the sixth inverter.
2. The circuit for accelerating the settling time of a long trace on a chip according to claim 1, wherein power sources connected to the first inverter, the second inverter, the third inverter and the sixth inverter are Vcc and ground is GND.
3. The circuit for accelerating the build-up time of a long trace on a chip according to claim 1, wherein the internal structures of the first inverter, the second inverter, the third inverter and the sixth inverter are not limited by the number and types of MOS transistors, and the function of the inverters is realized.

Description

Circuit for accelerating long wiring setup time in chip Technical Field The invention relates to the technical field of integrated circuits, in particular to a circuit for accelerating the long wiring establishment time in a chip. Background With the rapid development of electronic information technology, the density of integrated circuits and the number of conductor wires are continuously increased, so that the resistor-capacitor delay (RCdelay) seriously affects the operation speed of a chip, namely the establishment time of a next-stage circuit. Particularly in the large-scale Soc circuit design and the design of a high-frequency chip circuit, an excessively long wiring design often brings about excessively large RCloading, so that the response delay and the precision deviation of the chip are caused, and even the normal performance of the chip is influenced. However, due to the excessive chip scale, the design of long routing cannot be avoided, and the layout design can be realized by increasing the line width, adding shielding wires or adopting multi-layer metal stacked routing to reduce RC loading. However, when the layout design is not available, the acceleration of the next stage of circuit establishment time can be realized by improving the circuit design, so that the chip area is not excessively increased, and the influence of the long wiring RCLoading on the circuit performance can be skillfully avoided. Fig. 1 is a schematic diagram of a conventional logic circuit design structure, in which an output end of an inverter (11) is connected to an input end of an inverter (12), an output end of the inverter (12) is connected to an input end of an inverter (13), and an output end of the inverter (13) is an output end of a circuit, when a signal line (15) is too long, a large RCloading is brought, so that an inversion signal of the inverter (13) is delayed to reach, which affects opening of a subsequent circuit, even affects circuit performance, especially in a large-scale Soc chip circuit or a high-frequency circuit, and the effect of RCloading is particularly remarkable. Fig. 2 is a schematic diagram of a conventional long-wire delay compensation circuit in a chip, wherein an output end of an inverter (21) is connected with an input end of an inverter (22), an output end of the inverter (22) is connected with an input end of an inverter (23), an output end of the inverter (23) is an output end of a circuit, an output end of the inverter (23) is connected with an input end of an inverter (26), an input end of the inverter (26) is connected with an input end of the inverter (23) in a feedback manner, and a signal of a signal line (25) is enhanced and the time is accelerated through a feedback design of the inverter (26). However, the circuit still has the disadvantage that when the voltage level on the signal line (25) does not reach the inversion voltage of the inverter (23), the signal on the signal line (27) is just opposite to the expected signal, that is, when the signal on the signal line (27) maintains the state of "1" in the previous stage, the signal on the signal line (25) cannot be quickly established from the state of "0" to the state of "1" due to RCloading, during the period, the output state of the inverter (26) is "0", and the signal on the signal line (25) is quickly established from the state of "0" to the state of "1", so that the feedback signal collides with the signal wanted to be established on the signal line (25) during the period, and the establishment time of the signal state on the signal line (25) from the state of "0" to the state of "1" is prolonged, thereby influencing the response of the subsequent circuit. Conversely, when the signal on the signal line (27) maintains the state "0" of the previous stage, the signal on the signal line (25) cannot be quickly established from the "1" state to the "0" state because RCloading, during this period, the output state of the inverter (26) is "1", and the signal on the signal line (25) is quickly established from the "1" state to the "0" state, so that the feedback signal collides with the signal which is desired to be established on the signal line (25) during this period, resulting in a longer establishment time for establishing the signal state on the signal line (25) from the "1" state to the "0" state, which affects the response of the subsequent circuit. Disclosure of Invention The invention aims to provide a circuit for accelerating the long wiring establishment time in a chip so as to solve the problems in the background technology. In order to solve the technical problems, the invention provides a circuit for accelerating the long wiring time in a chip, which comprises a front-stage BUFFER circuit, a rear-stage KEEPER circuit, a first MOS device and a second MOS device, wherein the BUFFER circuit and the KEEPER circuit are connected in series; The BUFFER circuit comprises a first inverter and a second inverter, wherein th