CN-116030866-B - Edge word line data retention improvement for memory devices utilizing a half-round drain side select gate by pitch technique

Abstract

The invention provides a memory device and a method of operation. The device includes a memory cell connected to a word line including at least one edge word line and other data word lines. The memory cells are arranged in strings and configured to hold threshold voltages corresponding to data states. The strings are organized in rows and a control device is coupled to the word lines and the strings and identifies the at least one edge word line. The control device programs the memory cells of the string in a particular one of the rows and associated with the at least one edge word line to have a changed threshold voltage distribution for one or more of the data states during a programming operation as compared to the memory cells of the string not in the particular one of the rows and not associated with the at least one edge word line.

Inventors

• YANG XIANG
• A. PRAKASH
• S. MUKHERJEE

Assignees

• 桑迪士克科技有限责任公司

Dates

Publication Date

20260505

Application Date

20220525

Priority Date

20211027

Claims (20)

1. 1. A memory device, comprising: A memory cell connected to one of a plurality of word lines including at least one edge word line and a plurality of other data word lines and arranged in strings and configured to hold threshold voltages corresponding to one of a plurality of data states, the strings organized in rows, and A controller coupled to the plurality of word lines and the string and configured to: identifying the at least one edge word line, and The memory cells of the string in a particular one of the rows and associated with the at least one edge word line are programmed from an erased state to have a changed threshold voltage distribution for one or more of the plurality of data states during a programming operation as compared to the memory cells of the string not in the particular one of the rows and not associated with the at least one edge word line, the particular one of the rows comprising a semicircular row comprising memory holes partially cut by shallow hole etching.
2. 2. The memory device of claim 1, wherein the plurality of word lines and plurality of dielectric layers extend horizontally and overlie one another in an alternating fashion in a stack through which the strings extend vertically, the memory cells being connected in series between at least one drain side select gate transistor located on a drain side of each of the strings and connected to one of the plurality of bit lines and at least one source side select gate transistor located on a source side of each of the strings and connected to a source line, the at least one edge word line being disposed vertically above and immediately adjacent to the plurality of other data word lines.
3. 3. The memory device of claim 2, wherein the threshold voltage possible for each of the memory cells spans a threshold window, each of the memory cells configured to store a plurality of bits, the plurality of data states including the erased state at a first end of the threshold window and a plurality of programmed data states each corresponding to the threshold voltage higher than the threshold voltage associated with the erased state, the plurality of programmed data states including a highest data state at a second end of the threshold window opposite the first end and associated with the threshold voltage higher than the threshold voltage associated with at least one of the erased state and the plurality of programmed data states.
4. 4. The memory device of claim 3, wherein the rows comprise full-circular and semi-circular rows comprising memory holes forming the strings, the memory holes being partially cut by the shallow hole etches extending vertically into the stack, and wherein the controller is further configured to: applying each program pulse of a plurality of program pulses of progressively increasing magnitude in each of a plurality of loops to the plurality of other data word lines during the programming operation until the memory cell programmed to the highest data state and associated with the full circle row reaches a first highest verify voltage level of the highest data state; Applying each program pulse of the plurality of program pulses of progressively increasing magnitude in each of the plurality of loops to the at least one edge word line during the programming operation until the memory cell programmed to the highest data state associated with the semicircular row and the at least one edge word line reaches a second highest verify voltage level of the highest data state, the second highest verify voltage level being higher than the first highest verify voltage level, and While programming the memory cells associated with the at least one edge word line to block programming the memory cells in the string associated with the full circular row, simultaneously applying a inhibit bit line voltage to bit lines of the string of the plurality of bit lines coupled to the full circular row, and while programming the memory cells associated with the at least one edge word line to facilitate programming the memory cells in the string associated with the half circular row, applying a select bit line voltage to bit lines of the string of the plurality of bit lines coupled to the half circular row.
5. 5. The memory device of claim 3, wherein the rows comprise a full circle row and the semicircle row, the particular one of the rows being both the semicircle row and the full circle row, and the controller is further configured to: Applying each program pulse of a plurality of program pulses of progressively increasing magnitude in each of a plurality of loops to the plurality of other data word lines during the program operation until the memory cell programmed to the highest data state and associated with the plurality of other data word lines reaches a low highest verify voltage level of the highest data state, and Each program pulse of the plurality of program pulses that gradually increases in magnitude in each of the plurality of loops is applied to the at least one edge word line during the programming operation until the memory cell programmed to the highest data state associated with the at least one edge word line reaches a highest verify voltage level of the highest data state that is greater in magnitude than the low highest verify voltage level.
6. 6. The memory device of claim 3, wherein the rows comprise a full circle row and the semicircle row, the particular one of the rows being both the semicircle row and the full circle row, the plurality of bits comprising three bits, a total state quantity of the plurality of data states being eight, the plurality of program data states comprising first and second and third and fourth and fifth and sixth and seventh data states in order of increasing magnitude of the threshold voltage, the highest data state being the seventh data state, and the controller being further configured to: For the memory cells associated with the plurality of other data word lines and programmed to one of the first and third and fourth data states and fifth and sixth and seventh data states during the program operation, applying each of a plurality of program pulses to the plurality of other data word lines that gradually increase in magnitude in each of a plurality of loops during the program operation, until the memory cells programmed to the one of the first and second and third and fourth and fifth and sixth and seventh data states reach a low first voltage level and the fourth data state, respectively, of the first data state one of a low second voltage level of a data state and a low third voltage level of the third data state and a low fourth voltage level of the fourth data state and a low fifth voltage level of the fifth data state and a low sixth voltage level of the sixth data state and a low seventh voltage level of the seventh data state; For the memory cells associated with the at least one edge word line and programmed to one of the first and second data states and the third and fourth data states during the programming operation, applying each of the plurality of programming pulses of progressively increasing magnitude in each of the plurality of loops to the plurality of other data word lines during the programming operation until the memory cells programmed to the one of the first and second data states and the third and fourth data states reach one of the low first and second and third voltage levels of the first and second data states and the low fourth voltage level of the third and fourth data states, respectively, and For the memory cells associated with the at least one edge word line and programmed to one of the fifth and sixth data states and the seventh data state during the programming operation, each programming pulse of the plurality of programming pulses that gradually increases in magnitude in each of the plurality of loops is applied to the plurality of other data word lines during the programming operation until the memory cells programmed to the one of the fifth and sixth data states and the seventh data state reach one of a high fifth voltage level of the fifth and sixth data state and a high seventh voltage level of the seventh data state, respectively, the high fifth voltage level being greater in magnitude than the low fifth voltage level and the high sixth voltage level being greater in magnitude than the low sixth voltage level and the high seventh voltage level being greater in magnitude than the low seventh voltage level.
7. 7. The memory device of claim 3, wherein the rows comprise full-circular rows and the semi-circular rows comprising memory holes forming the strings, the memory holes being partially cut by shallow hole etches extending vertically into the stack, the particular one of the rows being both the semi-circular row and the full-circular row, the plurality of bits comprising three bits, a total state quantity of the plurality of data states being eight, the plurality of program data states comprising first and second and third and fourth and fifth and sixth and seventh data states in order of increasing in magnitude of the threshold voltage, the highest data state being the seventh data state, and the controller being further configured to: For the memory cells associated with the plurality of other data word lines and programmed to any of the plurality of programmed data states during the programming operation, applying a plurality of programming pulses to the plurality of other data word lines, the plurality of programming pulses gradually increasing in magnitude by a first programming step voltage in each of a plurality of loops; Applying a plurality of programming pulses to the at least one edge word line for the memory cells associated with the at least one edge word line and programmed to the third and second data states and the first data states during the programming operation, the plurality of programming pulses gradually increasing in magnitude the first programming step voltage in each of the plurality of cycles, and For the memory cells associated with the at least one edge word line and programmed to the seventh and sixth and fifth and fourth data states during the programming operation, the plurality of programming pulses are applied to the at least one edge word line, the plurality of programming pulses gradually increasing in magnitude in each of the plurality of loops by a second programming step voltage that is less than the first programming step voltage.
8. 8. A controller in communication with a memory device, the memory device comprising memory cells connected to one of a plurality of word lines, the plurality of word lines comprising at least one edge word line and a plurality of other data word lines, and arranged in strings and configured to maintain a threshold voltage corresponding to one of a plurality of data states, the strings organized in rows, the controller configured to: identifying the at least one edge word line, and The memory device is instructed to program the memory cells of the string in a particular one of the rows and associated with the at least one edge word line from an erased state to have a changed threshold voltage distribution for one or more of the plurality of data states during a programming operation as compared to the memory cells of the string not in the particular one of the rows and not associated with the at least one edge word line, the particular one of the rows comprising a semicircular row comprising memory holes partially cut by a shallow hole etch.
9. 9. The controller of claim 8, wherein the plurality of word lines and plurality of dielectric layers extend horizontally and overlap each other in an alternating fashion in a stack through which the strings extend vertically, the memory cells being connected in series between at least one drain side select gate transistor located on a drain side of each of the strings and connected to one of a plurality of bit lines and at least one source side select gate transistor located on a source side of each of the strings and connected to a source line, the at least one edge word line being disposed vertically above the plurality of other data word lines and in close proximity to the at least one drain side select gate transistor, the threshold voltages possible for each of the memory cells crossing a threshold window, each of the memory cells being configured to store a plurality of bits, the plurality of data states including the erased state at a first end of the threshold window and the programmed state and the plurality of data states each corresponding to the threshold voltages associated with the erased state and the one of the plurality of data states including the programmed state and the programmed state at the first end of the threshold window and the highest threshold voltage associated with the threshold voltage.
10. 10. The controller of claim 9, wherein the rows comprise full-circular and semi-circular rows comprising memory holes forming the strings, the memory holes being partially cut by the shallow hole etches extending vertically into the stack, and wherein the controller is further configured to: Each program pulse of a plurality of program pulses that instruct the memory device to progressively increase in magnitude in each of a plurality of cycles during the programming operation is applied to the plurality of other data word lines until the memory cell programmed to the highest data state and associated with the full circle row reaches a first highest verify voltage level of the highest data state; instructing the memory device to apply each program pulse of the plurality of program pulses of progressively increasing magnitude in each of the plurality of cycles to the at least one edge word line during the programming operation until the memory cell programmed to the highest data state associated with the semicircular row and the at least one edge word line reaches a second highest verify voltage level of the highest data state, the second highest verify voltage level being higher than the first highest verify voltage level, and The memory device is instructed to simultaneously apply a inhibit bit line voltage to a bit line of the plurality of bit lines coupled to the string of the full round row while programming the memory cells associated with the at least one edge word line to block programming the memory cells of the string associated with the full round row, and to apply a select bit line voltage to a bit line of the plurality of bit lines coupled to the string of the half round row while programming the memory cells of the string associated with the at least one edge word line to facilitate programming the memory cells of the string associated with the half round row.
11. 11. The controller of claim 9, wherein the rows comprise a full circle row and the semicircle row, the particular one of the rows being both the semicircle row and the full circle row, and the controller is further configured to: Each program pulse of a plurality of program pulses that instruct the memory device to progressively increase in magnitude in each of a plurality of cycles during the programming operation is applied to the plurality of other data word lines until the memory cell programmed to the highest data state and associated with the plurality of other data word lines reaches a low highest verify voltage level of the highest data state, and Each program pulse of the plurality of program pulses that instructs the memory device to gradually increase in magnitude in each of the plurality of loops during the programming operation is applied to the at least one edge word line until the memory cell programmed to the highest data state associated with the at least one edge word line reaches a high highest verify voltage level of the highest data state that is greater in magnitude than the low highest verify voltage level.
12. 12. The controller of claim 9, wherein the rows comprise a full circle row and the semicircle row, the particular one of the rows being both the semicircle row and the full circle row, the plurality of bits comprising three bits, the total state quantity of the plurality of data states being eight, the plurality of program data states comprising first and second and third and fourth and fifth and sixth and seventh data states in order of increasing magnitude of the threshold voltage, the highest data state being the seventh data state, and the controller being further configured to: For the memory cells associated with the plurality of other data word lines and programmed to one of the first and second and third and fourth data states and sixth and seventh data states during the programming operation, instructing the memory device to apply each of a plurality of programming pulses to the plurality of other data word lines that progressively increase in magnitude in each of a plurality of loops during the programming operation, until the memory cells programmed to the one of the first and second and third and fourth and fifth and sixth and seventh data states reach a low first voltage level and the fourth data state, respectively, of the first data state one of a low second voltage level of a data state and a low third voltage level of the third data state and a low fourth voltage level of the fourth data state and a low fifth voltage level of the fifth data state and a low sixth voltage level of the sixth data state and a low seventh voltage level of the seventh data state; For the memory cells associated with the at least one edge word line and programmed to one of the first and second data states and the third and fourth data states during the programming operation, instructing the memory device to apply each of the plurality of programming pulses of progressively increasing magnitude in each of the plurality of loops to the plurality of other data word lines during the programming operation until the memory cells programmed to the one of the first and second data states and the third and fourth data states reach one of the low first voltage level of the first data state and the low second voltage level of the second data state and the low third voltage level of the third data state and the low fourth voltage level of the fourth data state, respectively, and For the memory cells associated with the at least one edge word line and programmed to one of the fifth and sixth data states and the seventh data state during the programming operation, instructing the memory device to apply each programming pulse of the plurality of programming pulses that gradually increases in magnitude in each of the plurality of loops to the plurality of other data word lines during the programming operation until the memory cells programmed to the one of the fifth and sixth data states and the seventh data state reach one of a high fifth voltage level of the fifth and sixth data state and a high seventh voltage level of the seventh data state, respectively, the high fifth voltage level being greater in magnitude than the low fifth voltage level and the high sixth voltage level being greater in magnitude than the low sixth voltage level and the high seventh voltage level being greater in magnitude than the seventh voltage level.
13. 13. The controller of claim 9, wherein the rows comprise full-circular rows and the semi-circular rows comprising memory holes forming the strings, the memory holes being partially cut by shallow hole etches extending vertically into the stack, the particular one of the rows being both the semi-circular rows and the full-circular rows, the plurality of bits comprising three bits, a total state quantity of the plurality of data states being eight, the plurality of program data states comprising first and second and third and fourth and fifth and sixth and seventh data states in order of increasing in magnitude of the threshold voltage, the highest data state being the seventh data state, and the controller being further configured to: for the memory cells associated with the plurality of other data word lines and programmed to any of the plurality of program data states during the programming operation, instructing the memory device to apply a plurality of programming pulses to the plurality of other data word lines, the plurality of programming pulses gradually increasing in magnitude in each of a plurality of cycles by a first programming step voltage; For the memory cells associated with the at least one edge word line and programmed to the third and second data states and the first data state during the programming operation, instructing the memory device to apply a plurality of programming pulses to the at least one edge word line, the plurality of programming pulses gradually increasing in magnitude the first programming step voltage in each of the plurality of cycles, and For the memory cells associated with the at least one edge word line and programmed to the seventh and sixth data states and the fifth and fourth data states during the programming operation, instructing the memory device to apply the plurality of programming pulses to the at least one edge word line, the plurality of programming pulses gradually increasing in magnitude in each of the plurality of loops by a second programming step voltage that is less than the first programming step voltage.
14. 14. A method of operating a memory device comprising memory cells connected to one of a plurality of word lines including at least one edge word line and a plurality of other data word lines, and arranged in strings and configured to maintain a threshold voltage corresponding to one of a plurality of data states, the strings organized in rows, the method comprising the steps of: identifying the at least one edge word line, and The memory cells of the string in a particular one of the rows and associated with the at least one edge word line are programmed from an erased state to have a changed threshold voltage distribution for one or more of the plurality of data states during a programming operation as compared to the memory cells of the string not in the particular one of the rows and not associated with the at least one edge word line, the particular one of the rows comprising a semicircular row comprising memory holes partially cut by shallow hole etching.
15. 15. The method of claim 14, wherein the plurality of word lines and plurality of dielectric layers extend horizontally and overlie one another in an alternating fashion in a stack through which the strings extend vertically, the memory cells being connected in series between at least one drain side select gate transistor located on a drain side of each of the strings and connected to one of the plurality of bit lines and at least one source side select gate transistor located on a source side of each of the strings and connected to a source line, the at least one edge word line being disposed vertically above and immediately adjacent to the plurality of other data word lines.
16. 16. The method of claim 15, wherein the threshold voltage possible for each of the memory cells spans a threshold window, each of the memory cells configured to store a plurality of bits, the plurality of data states including the erased state at a first end of the threshold window and a plurality of programmed data states each corresponding to the threshold voltage higher than the threshold voltage associated with the erased state, the plurality of programmed data states including a highest data state at a second end of the threshold window opposite the first end and associated with the threshold voltage higher than the threshold voltage associated with at least one of the erased state and the plurality of programmed data states.
17. 17. The method of claim 16, wherein the rows comprise full-circle rows and the half-circle rows comprising memory holes forming the strings, the memory holes being partially cut by the shallow hole etches extending vertically into the stack, and the method further comprising the steps of: applying each program pulse of a plurality of program pulses of progressively increasing magnitude in each of a plurality of loops to the plurality of other data word lines during the programming operation until the memory cell programmed to the highest data state and associated with the full circle row reaches a first highest verify voltage level of the highest data state; Applying each program pulse of the plurality of program pulses of progressively increasing magnitude in each of the plurality of loops to the at least one edge word line during the programming operation until the memory cell programmed to the highest data state associated with the semicircular row and the at least one edge word line reaches a second highest verify voltage level of the highest data state, the second highest verify voltage level being higher than the first highest verify voltage level, and While programming the memory cells associated with the at least one edge word line to block programming the memory cells in the string associated with the full circular row, simultaneously applying a inhibit bit line voltage to bit lines of the string of the plurality of bit lines coupled to the full circular row, and while programming the memory cells associated with the at least one edge word line to facilitate programming the memory cells in the string associated with the half circular row, applying a select bit line voltage to bit lines of the string of the plurality of bit lines coupled to the half circular row.
18. 18. The method of claim 16, wherein the rows comprise full circle rows and the semicircle rows, the particular one of the rows being both the semicircle row and the full circle row, and the method further comprising the steps of: Applying each program pulse of a plurality of program pulses of progressively increasing magnitude in each of a plurality of loops to the plurality of other data word lines during the program operation until the memory cell programmed to the highest data state and associated with the plurality of other data word lines reaches a low highest verify voltage level of the highest data state, and Each program pulse of the plurality of program pulses that gradually increases in magnitude in each of the plurality of loops is applied to the at least one edge word line during the programming operation until the memory cell programmed to the highest data state associated with the at least one edge word line reaches a highest verify voltage level of the highest data state that is greater in magnitude than the low highest verify voltage level.
19. 19. The method of claim 16, wherein the rows comprise a full circle row and the semicircle row, the particular one of the rows being both the semicircle row and the full circle row, the plurality of bits comprising three bits, a total state quantity of the plurality of data states being eight, the plurality of program data states comprising first and second and third and fourth and fifth and sixth and seventh data states in order of increasing magnitude of the threshold voltage, the highest data state being the seventh data state, and the method further comprising the steps of: For the memory cells associated with the plurality of other data word lines and programmed to one of the first and third and fourth data states and fifth and sixth and seventh data states during the program operation, applying each of a plurality of program pulses to the plurality of other data word lines that gradually increase in magnitude in each of a plurality of loops during the program operation, until the memory cells programmed to the one of the first and second and third and fourth and fifth and sixth and seventh data states reach a low first voltage level and the fourth data state, respectively, of the first data state one of a low second voltage level of a data state and a low third voltage level of the third data state and a low fourth voltage level of the fourth data state and a low fifth voltage level of the fifth data state and a low sixth voltage level of the sixth data state and a low seventh voltage level of the seventh data state; For the memory cells associated with the at least one edge word line and programmed to one of the first and second data states and the third and fourth data states during the programming operation, applying each of the plurality of programming pulses of progressively increasing magnitude in each of the plurality of loops to the plurality of other data word lines during the programming operation until the memory cells programmed to the one of the first and second data states and the third and fourth data states reach one of the low first and second and third voltage levels of the first and second data states and the low fourth voltage level of the third and fourth data states, respectively, and For the memory cells associated with the at least one edge word line and programmed to one of the fifth and sixth data states and the seventh data state during the programming operation, each programming pulse of the plurality of programming pulses that gradually increases in magnitude in each of the plurality of loops is applied to the plurality of other data word lines during the programming operation until the memory cells programmed to the one of the fifth and sixth data states and the seventh data state reach one of a high fifth voltage level of the fifth and sixth data state and a high seventh voltage level of the seventh data state, respectively, the high fifth voltage level being greater in magnitude than the low fifth voltage level and the high sixth voltage level being greater in magnitude than the low sixth voltage level and the high seventh voltage level being greater in magnitude than the low seventh voltage level.
20. 20. The method of claim 16, wherein the rows comprise a full circle row and the semicircle row, the particular one of the rows being both the semicircle row and the full circle row, the plurality of bits comprising three bits, a total state quantity of the plurality of data states being eight, the plurality of program data states comprising first and second and third and fourth and fifth and sixth and seventh data states in order of increasing magnitude of the threshold voltage, the highest data state being the seventh data state, and the method further comprising the steps of: For the memory cells associated with the plurality of other data word lines and programmed to any of the plurality of programmed data states during the programming operation, applying a plurality of programming pulses to the plurality of other data word lines, the plurality of programming pulses gradually increasing in magnitude by a first programming step voltage in each of a plurality of loops; Applying a plurality of programming pulses to the at least one edge word line for the memory cells associated with the at least one edge word line and programmed to the third and second data states and the first data states during the programming operation, the plurality of programming pulses gradually increasing in magnitude the first programming step voltage in each of the plurality of cycles, and For the memory cells associated with the at least one edge word line and programmed to the seventh and sixth and fifth and fourth data states during the programming operation, the plurality of programming pulses are applied to the at least one edge word line, the plurality of programming pulses gradually increasing in magnitude in each of the plurality of loops by a second programming step voltage that is less than the first programming step voltage.

Description

Edge word line data retention improvement for memory devices utilizing a half-round drain side select gate by pitch technique Technical Field The present application relates to a nonvolatile memory device and operation of the nonvolatile memory device. Background This section provides background information related to the technology associated with the present disclosure and, thus, is not necessarily prior art. Semicircular drain side select gate ("SC-SGD") memory technology provides several advantages, including reduced die size. To produce SC-SGD, etching techniques are used to cut the memory holes, giving them a semicircular shape, and to divide the blocks or rows into strings. Depending on the process used to form the SC-SGD, some inefficiency may occur. For example, cutting the memory hole will remove at least some portions of the SC-SGD, such as the metal layer that would otherwise shield the electric field from the channel and/or charge-trapping layer. Thus, the SC-SGD may be affected by "adjacent" electric fields, resulting in parasitic transistor leakage along the SC-SGD transistor. In some cases, this results in the sense amplifier incorrectly determining that the SC-SGD is conducting, which may affect certain sense operations. Further, due to etch variations, some dies may be cut into SGD layers, while other dies may be cut into layers forming dummy word lines. Therefore, a data retention problem may occur due to the proximity of the cutouts to the data word lines. Accordingly, there is a need for improved non-volatile memory devices and methods of operation. Disclosure of Invention This section provides a general summary of the disclosure, and is not a comprehensive disclosure of its full scope or all of its features and advantages. It is an object of the present disclosure to provide a memory device and a method of operating the memory device that address and overcome the above-described drawbacks. Accordingly, it is an aspect of the present disclosure to provide a memory device including a memory cell connected to one of a plurality of word lines including at least one edge word line and a plurality of other data word lines. The memory cells are arranged in strings and configured to maintain a threshold voltage corresponding to one of a plurality of data states. The strings are organized in rows, and a control device is coupled to the plurality of word lines and the strings. The control device is configured to identify the at least one edge word line. The control device programs the memory cells of the string in a particular one of the rows and associated with the at least one edge word line to have a changed threshold voltage distribution for one or more of the plurality of data states during a programming operation as compared to the memory cells of the string not in the particular one of the rows and not associated with the at least one edge word line. According to another aspect of the present disclosure, there is also provided a controller in communication with a memory device including a memory cell connected to one of a plurality of word lines including at least one edge word line and a plurality of other data word lines. The memory cells are arranged in strings and configured to maintain a threshold voltage corresponding to one of a plurality of data states. The strings are organized in rows. The controller is configured to identify the at least one edge word line. The controller is also configured to instruct the memory device to program the memory cells of the string in a particular one of the rows and associated with the at least one edge word line to have a changed threshold voltage distribution for one or more of the plurality of data states during a programming operation as compared to the memory cells of the string not in the particular one of the rows and not associated with the at least one edge word line. According to an additional aspect of the present disclosure, a method of operating a memory device is provided. The memory device includes a memory cell connected to one of a plurality of word lines including at least one edge word line and a plurality of other data word lines. The memory cells are arranged in strings and configured to maintain a threshold voltage corresponding to one of a plurality of data states. The strings are organized in rows. The method includes the step of identifying the at least one edge word line. The method also includes programming the memory cells of the string in a particular one of the rows and associated with the at least one edge word line to have a changed threshold voltage distribution for one or more of the plurality of data states during a programming operation as compared to the memory cells of the string not in the particular one of the rows and not associated with the at least one edge word line. Further areas of applicability will become apparent from the description provided herein. The description and specific examples in this sum