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CN-116030870-B - Switch control circuit, chip and electronic equipment

CN116030870BCN 116030870 BCN116030870 BCN 116030870BCN-116030870-B

Abstract

The switch control circuit comprises a first transistor, a second transistor, a third transistor, an enabling logic circuit, a first control circuit, a second control circuit, a slope control circuit and a feedback control circuit, wherein the control electrode of the first transistor is controlled by the first control circuit, the first control circuit controls the on and off of the first transistor, the control electrode of the second transistor is controlled by the second control circuit, the second control circuit controls the on and off of the second transistor, the control electrode of the third transistor is controlled by the slope control circuit, the slope control circuit controls the rising slope of an AVDD voltage by setting the capacitance value of a capacitor array, and the enabling logic circuit controls the on and off of the first control circuit, the second control circuit and the slope control circuit according to an enabling signal and a feedback signal.

Inventors

  • CHEN RUIPENG
  • HUANG LINGHUA

Assignees

  • 圣邦微电子（北京）股份有限公司

Dates

Publication Date
20260512
Application Date
20221230

Claims (11)

  1. 1. The switch control circuit is characterized by comprising a first transistor, a second transistor, a third transistor, an enabling logic circuit, a first control circuit, a second control circuit, a slope control circuit and a feedback control circuit, wherein: A first pole of the first transistor is coupled to an input voltage terminal, a second pole of the first transistor is coupled to an AVDD terminal of the efuse, a control pole of the first transistor is controlled by the first control circuit, and the first control circuit is configured to control the first transistor to be turned on and off; A first pole of the second transistor is coupled to the input voltage terminal, a second pole of the second transistor is coupled to a second pole of the third transistor, and the first pole of the third transistor is respectively coupled to the AVDD terminal and an input terminal of the feedback control circuit, and the feedback control circuit is configured to output a feedback signal to the enable logic circuit via an output terminal; A control electrode of the second transistor is controlled by the second control circuit, and the second control circuit is configured to control the second transistor to be turned on and off; the control electrode of the third transistor is controlled by the slope control circuit, and the slope control circuit is configured to control the on and off of the third transistor and control the rising slope of an AVDD voltage by setting the capacitance value of a capacitor array in the slope control circuit, wherein the AVDD voltage is the voltage of the AVDD terminal; The enable logic circuit is configured to control on and off of the first control circuit, the second control circuit, and the slope control circuit according to an input enable signal and the feedback signal.
  2. 2. The switch control circuit of claim 1, further comprising a first resistor and a first capacitor, wherein the first resistor and the first capacitor are connected in parallel, and wherein a first end of the parallel is coupled to the AVDD terminal; The input voltage terminal, the first transistor and the AVDD terminal form a main channel, and the first control circuit is configured to control the on and off of the main channel by controlling the on and off of the first transistor; The input voltage end, the second transistor, the third transistor and the AVDD end form a secondary path, and the second control circuit is configured to control the on and off of the secondary path by controlling the on and off of the second transistor; the enable logic circuit is further configured to control the opening and closing of the main and sub-paths by controlling the opening and closing of the first and second control circuits.
  3. 3. The switch control circuit of claim 1, wherein the enable logic circuit comprises a first delay, a second delay, a first and gate, a first inverter, and a second and gate; the input end of the first delay device is coupled with an enabling signal end, the output end of the first delay device is coupled with the first input end of the first AND gate, and the enabling signal is input through the enabling signal end; The input end of the second delay device is coupled with the output end of the feedback control circuit, and the output end of the second delay device is respectively coupled with the second input end of the first AND gate and the input end of the first inverter; The first AND gate is configured to output a first switch enable signal from an output terminal to the first control circuit; The first input end of the second AND gate is coupled to the output end of the first inverter, the second input end of the second AND gate is coupled to the enable signal end, and the second AND gate is configured to output a second switch enable signal from the output end to the second control circuit.
  4. 4. The switch control circuit of claim 1, wherein the first control circuit comprises a fourth transistor, a second resistor, a second inverter, a fifth transistor, and a third resistor; The enable logic circuit is further configured to output a first switch enable signal from a first output terminal to a control electrode of the fourth transistor and an input terminal of the second inverter, respectively; The first electrode of the fourth transistor is grounded, the second electrode of the fourth transistor is coupled with the control electrode of the first transistor and the first end of the second resistor respectively, and the second end of the second resistor is coupled with the first electrode of the first transistor; the output end of the second inverter is coupled to the control electrode of the fifth transistor, the first electrode of the fifth transistor is grounded, the second electrode of the fifth transistor is coupled to the first end of the third resistor, and the second end of the third resistor is coupled to the second electrode of the first fourth transistor.
  5. 5. The switch control circuit of claim 1, wherein the second control circuit comprises a sixth transistor and a fourth resistor; the enable logic circuit is further configured to output a second switch enable signal from a second output terminal to the control electrode of the sixth transistor; the first electrode of the sixth transistor is grounded, the second electrode of the sixth transistor is coupled to the control electrode of the second transistor and the first end of the fourth resistor, respectively, and the second end of the fourth resistor is coupled to the first electrode of the second transistor.
  6. 6. The switch control circuit of claim 1, wherein the slope control circuit comprises a current source, a first control switch, a third inverter, a capacitor array, and a second control switch; The enabling logic circuit is further configured to output a second switch enabling signal from a second output end to the input ends of the first control switch and the third inverter respectively, control the opening and closing of the first control switch, and control the opening and closing of the second control switch through the output end of the third inverter; a first end of the first control switch is coupled with a second pole of the second transistor and a second pole of the third transistor respectively, and a second end of the first control switch is coupled with a first end of the current source; The first end of the second control switch is coupled with the second end of the current source, and the second end of the second control switch is respectively coupled with the second end of the capacitor array and the grounding end; The first end of the capacitor array is respectively coupled with the control electrode of the third transistor and the second end of the current source, the capacitor array is configured to be controlled by an external digital control signal, a capacitance value is set according to binary coded numbers provided by the external digital control signal, and the rising slope of the AVDD voltage is controlled before the programming and writing stage of the efuse based on the capacitance value; the current source is configured to charge the set-up capacitive array.
  7. 7. The switch control circuit of claim 6 wherein the external digital control signal provides a binary coded number of bits N, wherein N is an integer greater than 1; the capacitor array comprises N second capacitors and N corresponding third control switches, each second capacitor and the corresponding third control switch are connected in series to form a capacitor-switch group, and the N capacitor-switch groups are connected in parallel to form the capacitor array; a first terminal of each capacitor-switch group is coupled to the control electrode of the third transistor and the second terminal of the current source, respectively, and a second terminal of each capacitor-switch group is grounded.
  8. 8. The switch control circuit of claim 2, wherein the feedback control circuit comprises a first voltage dividing resistor, a second voltage dividing resistor, a voltage comparator, a fourth control switch, and a power supply; The enabling logic circuit is further configured to output a second switch enabling signal from a second output terminal to an input terminal of a third inverter, and control opening and closing of the fourth control switch via the output terminal of the third inverter; the first end of the fourth control switch is respectively coupled with the inverting end of the voltage comparator and the positive electrode of the power supply, the second end of the fourth control switch is respectively coupled with the negative electrode of the power supply and the grounding end, and the power supply is configured to provide reference voltage for the inverting end of the voltage comparator; a first end of the first voltage dividing resistor is respectively coupled with a first pole of the third transistor and the AVDD end, a second end of the first voltage dividing resistor is respectively coupled with a same-phase end of the voltage comparator and a first end of the second voltage dividing resistor, and a second end of the second voltage dividing resistor is grounded; the voltage comparator is configured to output a feedback signal from an output terminal to the enable logic circuit, and control a first switch enable signal and a second switch enable signal output by the enable logic circuit.
  9. 9. The switch control circuit of claim 8, wherein the feedback control circuit further comprises an or gate and a timer; The first input end of the OR gate is coupled with the output end of the third inverter; the first end of the timer is coupled to the output end of the voltage comparator, the second end of the timer is coupled to the second input end of the OR gate, and the timer is configured to control the fourth control switch to be in a closed state to open the main channel when the enable signal is at an active level and the main channel is not opened within a preset duration.
  10. 10. A chip comprising the switch control circuit of any one of claims 1-9.
  11. 11. An electronic device comprising the chip of claim 10.

Description

Switch control circuit, chip and electronic equipment Technical Field The disclosure relates to the technical field of integrated circuits, and in particular relates to a switch control circuit, a chip and electronic equipment. Background The efuse is generally an IP provided by a chip manufacturer, and is a nonvolatile one-time programmable memory, so that the chip to be produced can be embedded with the efuse IP in order to improve the safety factor of chip design and the yield of chip mass production test. In the programming and programming stage, the AVDD end of the efuse can draw larger current, and in some application scenes, the AVDD end needs to multiplex pins of a chip to be produced and is controlled by introducing an independent power supply from outside. In order to reduce the overall chip power consumption and avoid affecting other functions of the chip when multiplexing pins, a switch and a control circuit for the switch are required to be added between an AVDD terminal and an external power supply, and in order to protect the efuse IP, the rising slope of the AVDD voltage cannot be too large, and the added switch control circuit is required to enable the rising slope of the AVDD voltage to be controllable. However, it is difficult for the switch control circuit in the related art to control the rising slope of the AVDD voltage, resulting in the possibility that the efuse IP may fail. Disclosure of Invention The present disclosure is directed to a switch control circuit, a chip and an electronic device, and aims to solve the problem that in the related art, the switch control circuit is difficult to control the rising slope of the AVDD voltage, resulting in possible failure of the efuse IP. In order to achieve the above object, a first aspect of the present disclosure provides a switch control circuit including a first transistor, a second transistor, a third transistor, an enable logic circuit, a first control circuit, a second control circuit, a slope control circuit, and a feedback control circuit, wherein: A first pole of the first transistor is coupled to the input voltage terminal, a second pole of the first transistor is coupled to the AVDD terminal of the efuse, and a control pole of the first transistor is controlled by a first control circuit configured to control the first transistor to be turned on and off; The first pole of the second transistor is coupled with the input voltage end, the second pole of the second transistor is coupled with the second pole of the third transistor, the first pole of the third transistor is respectively coupled with the AVDD end and the input end of the feedback control circuit, and the feedback control circuit is configured to output a feedback signal to the enabling logic circuit through the output end; the control electrode of the second transistor is controlled by a second control circuit, and the second control circuit is configured to control the on and off of the second transistor; The control electrode of the third transistor is controlled by a slope control circuit, and the slope control circuit is configured to control the on and off of the third transistor and control the rising slope of the AVDD voltage by setting the capacitance value of the capacitor array in the slope control circuit, wherein the AVDD voltage is the voltage of the AVDD terminal; The enable logic circuit is configured to control the first control circuit, the second control circuit and the slope control circuit to be turned on and off according to the input enable signal and the feedback signal. Optionally, the switch control circuit further includes a first resistor and a first capacitor, wherein the first resistor and the first capacitor are connected in parallel, and a first end after being connected in parallel is coupled to the AVDD end; The input voltage end, the first transistor and the AVDD end form a main channel, and the first control circuit is configured to control the on and off of the main channel by controlling the on and off of the first transistor; the input voltage end, the second transistor, the third transistor and the AVDD end form a secondary path, and the second control circuit is configured to control the on and off of the secondary path by controlling the on and off of the second transistor; the enable logic circuit is further configured to control the opening and closing of the main path and the sub path by controlling the opening and closing of the first control circuit and the second control circuit. Optionally, the enabling logic circuit includes a first delay, a second delay, a first and gate, a first inverter, and a second and gate; the input end of the first delay device is coupled with the enabling signal end, and the output end of the first delay device is coupled with the first input end of the first AND gate, wherein the enabling signal is input through the enabling signal end; the input end of the second delay device is coupled with