CN-116048868-B - Code generation method, device, equipment and storage medium

CN116048868BCN 116048868 BCN116048868 BCN 116048868BCN-116048868-B

Abstract

The application provides a code generation method, a device, equipment and a storage medium, wherein the method comprises the steps of obtaining configuration parameters corresponding to a target algorithm to be processed, wherein the configuration parameters comprise a generation polynomial of the target algorithm and an input data bit width; and calculating the coded data bit by bit according to the generating polynomial, and determining a circuit structure expression corresponding to each bit of the coded data. The application takes the bit type algorithm as the basis, obtains the coding data coded by the algorithm according to the configuration parameters, carries out bit-by-bit calculation on the coding data, generates the circuit structure expression of the algorithm, realizes the automatic deduction of the circuit structure corresponding to the algorithm, and improves the circuit design efficiency.

Inventors

WANG SHAOFENG
SONG MINGHUI
ZENG FENG

Assignees

海光信息技术股份有限公司

Dates

Publication Date: 20260508
Application Date: 20211223

Claims (19)

1. A code generation method, comprising: Acquiring configuration parameters corresponding to a target algorithm to be processed, wherein the configuration parameters comprise a generating polynomial of the target algorithm, an input data bit width, an input inversion flag bit and an initial value; Generating coded data matched with the bit width of the input data according to the configuration parameters; Performing bit-by-bit calculation on the encoded data according to the generating polynomial, and determining a circuit structure expression corresponding to each bit of the encoded data; wherein generating encoded data matching the input data bit width according to the configuration parameters comprises: generating input data corresponding to the target algorithm according to the bit width of the input data; Processing the input data according to the input inversion flag bit, wherein if the input inversion flag bit is 1, data inversion is performed on the input data according to bytes; Adding a preset coding value at the tail of the processed input data; And performing exclusive OR operation on the input data added with the coding value and the initial value to obtain the coding data.
2. The method according to claim 1, wherein the obtaining the configuration parameters corresponding to the target algorithm to be processed includes: When the target algorithm to be processed is received, judging whether the target algorithm exists in a database; when the target algorithm exists in the database, acquiring a first parameter of the target algorithm input by a user, extracting a preset parameter corresponding to the target algorithm prestored in the database, and taking the first parameter and the preset parameter as the configuration parameter.
3. The method of claim 2, wherein the first parameter comprises one or more of an input data bit width of the target algorithm, a target algorithm identification, and verification data.
4. The method of claim 3, wherein the predetermined parameters include one or more of a generator polynomial, an initial value, an input inversion flag, an output inversion flag, and an output exclusive-or value of the target algorithm.
5. The method according to claim 2, wherein the obtaining the configuration parameters corresponding to the target algorithm to be processed further comprises: When the target algorithm does not exist in the database, acquiring the user-defined parameter of the target algorithm input by a user, and taking the user-defined parameter as the configuration parameter of the target algorithm.
6. The method of claim 5, wherein the custom parameters include: One or more of an input data bit width, check data, a generator polynomial of the target algorithm, an initial value, an input inversion flag bit, an output inversion flag bit, and an output exclusive-or value of the target algorithm.
7. The method of claim 1, wherein the calculating the encoded data bit by bit according to the generator polynomial to determine a circuit structure expression corresponding to each bit of the encoded data comprises: Shifting the data in the coded data to the left by a specified bit to obtain a shifted-out data group; If the highest bit in the shifted-out data set is 0, shifting the whole shifted-out data set by one bit left, and shifting one bit left from the rest coded data into the shifted-out data set; If the highest bit in the shifted-out data set is not 0, carrying out exclusive-or operation on the data in the shifted-out data set and the generator polynomial of the target algorithm according to the bits, shifting one bit left by the result of the exclusive-or operation, storing the shifted-out data set, and shifting one bit left from the rest of coded data into the shifted-out data set; And determining the circuit structure expression corresponding to the target algorithm according to the shifted-out data set obtained after shifting, and calculating the data of each bit in the encoded data by adopting the mode to obtain a plurality of circuit structure expressions corresponding to the target algorithm.
8. The method of claim 7, wherein determining the circuit structure expression corresponding to the target algorithm according to the shifted-out data set obtained after shifting includes: And simplifying the shifted-out data set obtained after shifting by adopting a Kano diagram to obtain the circuit structure expression corresponding to the target algorithm.
9. The method as recited in claim 7, further comprising: and carrying out output processing on the circuit structure expression according to the configuration parameters, and outputting a final circuit structure expression corresponding to the target algorithm.
10. The method of claim 1, wherein the configuration parameters further comprise verification data for the target algorithm, the method further comprising: And carrying the verification data into a plurality of circuit structure expressions to obtain verification values output by the circuit structure expressions, and comparing the verification values with preset standard values to verify the accuracy of the circuit structure expressions.
11. The method of claim 1, further comprising generating a code file for the target algorithm based on the circuit structure expression.
12. A code generating apparatus, comprising: the parameter acquisition module is used for acquiring configuration parameters corresponding to a target algorithm to be processed, wherein the configuration parameters comprise a generating polynomial of the target algorithm, an input data bit width, an input inversion flag bit and an initial value; The data generation module is used for generating coded data matched with the bit width of the input data according to the configuration parameters; the expression determining module is used for carrying out bit-by-bit calculation on the encoded data according to the generating polynomial and determining a circuit structure expression corresponding to each bit of the encoded data; Wherein, the data generation module is used for: generating input data corresponding to the target algorithm according to the bit width of the input data; Processing the input data according to the input inversion flag bit, wherein if the input inversion flag bit is 1, data inversion is performed on the input data according to bytes; Adding a preset coding value at the tail of the processed input data; And performing exclusive OR operation on the input data added with the coding value and the initial value to obtain the coding data.
13. The apparatus of claim 12, wherein the parameter acquisition module is configured to: When the target algorithm to be processed is received, judging whether the target algorithm exists in a database; When the target algorithm exists in the database, acquiring a first parameter of the target algorithm input by a user, extracting a preset parameter corresponding to the target algorithm prestored in the database, and taking the first parameter and the preset parameter as the configuration parameter; the first parameter comprises one or more of input data bit width of the target algorithm, target algorithm identification and check data; The preset parameters comprise one or more of a generator polynomial, an initial value, an input inversion flag bit, an output inversion flag bit and an output exclusive or value of the target algorithm.
14. The apparatus of claim 13, wherein the parameter acquisition module is configured to: When the target algorithm does not exist in the database, acquiring a user-defined parameter of the target algorithm input by a user, and taking the user-defined parameter as a configuration parameter of the target algorithm; The custom parameters comprise one or more of input data bit width, check data of the target algorithm, a generator polynomial of the target algorithm, an initial value, an input inversion flag bit, an output inversion flag bit and an output exclusive-or value.
15. The apparatus of claim 12, wherein the expression determination module is to: Shifting the data in the coded data to the left by a specified bit to obtain a shifted-out data group; If the highest bit in the shifted-out data set is 0, shifting the whole shifted-out data set by one bit left, and shifting one bit left from the rest coded data into the shifted-out data set; If the highest bit in the shifted-out data set is not 0, carrying out exclusive-or operation on the data in the shifted-out data set and the generator polynomial of the target algorithm according to the bits, shifting one bit left by the result of the exclusive-or operation, storing the shifted-out data set, and shifting one bit left from the rest of coded data into the shifted-out data set; And determining the circuit structure expression corresponding to the target algorithm according to the shifted-out data set obtained after shifting, and calculating the data of each bit in the encoded data by adopting the mode to obtain a plurality of circuit structure expressions corresponding to the target algorithm.
16. The apparatus of claim 12, wherein the configuration parameters further comprise verification data for the target algorithm, the apparatus further comprising: And the expression verification module is used for bringing the verification data into a plurality of circuit structure expressions to obtain verification values output by the circuit structure expressions, and comparing the verification values with preset standard values to verify the accuracy of the circuit structure expressions.
17. The apparatus of claim 12, wherein the apparatus further comprises: and the code generation module is used for generating a code file of the target algorithm according to the circuit structure expression.
18. An electronic device, comprising: a memory for storing a computer program; A processor for executing the computer program to implement the method of any one of claims 1 to 11.
19. A non-transitory electronic device readable storage medium comprising a program that, when executed by an electronic device, causes the electronic device to perform the method of any one of claims 1-11.

Description

Code generation method, device, equipment and storage medium Technical Field The present application relates to the field of communications technologies, and in particular, to a code generation method, apparatus, device, and storage medium. Background The CRC (Cyclic-Redundancy-Check) Check code is a commonly used Check code with the capability of error detection and error correction, and is widely applied to data Check of synchronous communication between an external memory and a computer. The principle of CRC checking is to establish a contracted relation between data bits and check bits by using a specific mathematical operation, by which a CRC check code is generated at a transmitting end and transmitted to a receiving end together with the CRC check code attached to data to be transmitted. The receiving end performs CRC check on the received data by using the same mathematical operation, so as to judge whether the data has errors in the transmission process. In ASIC (Application-Specific-Integrated-Circuit) chip design, in order to ensure the transmission correctness of data, it is often necessary to perform CRC check on the data, and in order to obtain higher speed, the CRC check code is not generated by software calculation, but is directly implemented by a hardware Circuit. In the hardware implementation process of the CRC check circuit, a common scenario is to derive a circuit structural expression of the CRC check code for a data block determined by a certain bit width, and implement circuit design using a hardware description language. Aiming at different CRC algorithms and different data lengths, the implementation of the CRC circuit is different, and the process of solving the CRC circuit by using a manual derivation method is very complicated, and is time-consuming and labor-consuming. Disclosure of Invention The embodiment of the application aims to provide a code generation method, a device, equipment and a storage medium, which are based on a bit type algorithm, obtain coded data coded by the algorithm according to configuration parameters, calculate the coded data bit by bit, generate a circuit structure expression of the algorithm, realize automatic deduction of a circuit structure corresponding to the algorithm and improve circuit design efficiency. The first aspect of the embodiment of the application provides a code generation method, which comprises the steps of obtaining configuration parameters corresponding to a target algorithm to be processed, wherein the configuration parameters comprise a generation polynomial of the target algorithm and an input data bit width, generating coding data matched with the input data bit width according to the configuration parameters, calculating the coding data bit by bit according to the generation polynomial, and determining a circuit structure expression corresponding to each bit of the coding data. In an embodiment, the obtaining the configuration parameters corresponding to the target algorithm to be processed includes judging whether the target algorithm exists in a database when the target algorithm to be processed is received, obtaining first parameters of the target algorithm input by a user when the target algorithm exists in the database, extracting preset parameters corresponding to the target algorithm pre-stored in the database, and taking the first parameters and the preset parameters as the configuration parameters. In one embodiment, the first parameter includes one or more of an input data bit width of the target algorithm, a target algorithm identification, and verification data. In one embodiment, the predetermined parameters include one or more of a generator polynomial, an initial value, an input inversion flag, an output inversion flag, and an output exclusive-or value of the target algorithm. In an embodiment, the obtaining the configuration parameter corresponding to the target algorithm to be processed further includes obtaining a user-defined parameter of the target algorithm entered by a user when the target algorithm does not exist in the database, and taking the user-defined parameter as the configuration parameter of the target algorithm. In one embodiment, the custom parameters include one or more of an input data bit width of the target algorithm, check data, a generator polynomial of the target algorithm, an initial value, an input inversion flag bit, an output inversion flag bit, and an output exclusive-or value. In an embodiment, the generating the encoded data matched with the bit width of the input data according to the configuration parameters includes generating the input data corresponding to the target algorithm according to the bit width of the input data, processing the input data according to the input inversion flag bit, adding a preset encoded value at the end of the processed input data, and performing exclusive-or operation on the input data added with the encoded value and the initial value to obta