CN-116049073-B - AXI bus-based implementation method for custom DMA IP core

Abstract

The invention discloses an AXI bus-based implementation method of a custom DMAIP core, which is applied to Zynq7000 series of Xilinx company. The method comprises an IP core establishment process of a PS-to-PL channel and an IP core establishment process of a PL-to-PS channel, wherein the establishment of the PS-to-PL channel mainly comprises the steps of establishing an IP core, receiving and processing PS-end control data through SOO_AXI, receiving and processing PS-end high-speed data through MOO_AXI, transmitting the high-speed data to the PL end through M_AXIS and the like. The establishment of the PL to PS channel mainly comprises the steps of creating an IP core, receiving and processing PS end control data through SOO_AXI, receiving and processing PL end high-speed data through an S_AXIS port, and sending the high-speed data to the PS end through M00_AXI. The AXI bus-based custom DMAIP core realized by the invention has the advantages of customizable interface and good flexibility.

Inventors

• XIE JIAXI
• CHENG ZHIHONG
• ZHU YONGQIANG
• CHEN ZHEN
• ZHANG RUNDONG
• LI FAMING

Assignees

• 中国电子科技集团公司第五十四研究所

Dates

Publication Date

20260505

Application Date

20221220

Claims (1)

1. 1. The implementation method of the custom DMAIP core based on the AXI bus is characterized by comprising an IP core establishment process from a PS channel to a PL channel and an IP core establishment process from the PL channel to the PS channel; the IP core establishment process from the PS channel to the PL channel is as follows: s1, creating an IP core with an AXI4 interface, and adding an S00 AXI port, an M00 AXI port and an M_AXIS port; S2, receiving PS end control data through an SOO_AXI port, wherein a write address channel signal in the SOO_AXI port is used as a starting address for receiving the control data, a write data channel signal is used as the received control data, and the address is shifted by a fixed byte after each data reception; analyzing the received control data, sending the analyzed control data information to an MOO_AXI port as a base address and total data length of PS-end high-speed data received by a PL end, wherein the analyzed control data information comprises a 0 th bit data effective signal, a1 st to 32 nd bit data length signal and a 33 rd to 64 th bit data base address signal; S3, receiving high-speed data of a PS end through a MOO_AXI port, wherein a PL end is a host, the PS end is a slave, taking a data base address signal as a read address channel signal of the MOO_AXI port, receiving high-speed data from the read data channel signal, receiving a total length data length signal, calculating an effective mark signal, a signal turning signal and an end mark signal required by a time sequence of an M_AXIS port through a data effective signal, converting the high-speed data, the effective mark signal, the signal turning signal and the end mark signal into a time sequence of M_AXIS, and transmitting the converted data to the PL end through the M_AXIS port; The IP core establishment process from the PL channel to the PS channel is as follows: s4, creating an IP core with an AXI4 interface, and adding an S00 AXI port, an M00 AXI port and an S_AXIS port; S5, receiving PS end control data through an SOO_AXI port, using a write address channel signal in the SOO_AXI port as a starting address for receiving the control data, using the write address channel signal as the received control data, shifting the address of the received control data by a fixed byte after each time of receiving the control data, analyzing the received control data, and sending analyzed control data information to the MOO_AXI port, wherein the analyzed control data information comprises a base address and total data length information required by a PL end for sending PS end high-speed data; S6, receiving PL end high-speed data through the S_AXIS port, wherein the PL end high-speed data comprises a high-speed data signal, an effective mark signal, a signal turning signal and an end mark signal, transmitting the high-speed data to the MOO_AXI port, and transmitting the high-speed data to the PS end at the MOO_AXI port according to the analyzed control data information.

Description

AXI bus-based implementation method for custom DMA IP core Technical Field The invention relates to Zynq 7000 series of Xilinx company, in particular to a method for realizing a custom DMA IP core based on an AXI bus, which is applied to the Zynq 7000 series. Background Zynq 7000 is a programmable system-on-chip serial chip designed and produced by Xilinx company, the serial product embeds a programmable logic and ARM Cortex A9 dual-core hard core processor in a single chip, the serial product mainly comprises a Processor System (PS) and a Programmable Logic (PL), the two parts are communicated through a high-speed AXI bus, a large amount of data transmission can be directly transmitted to a system memory without a CPU through a Direct Memory Access (DMA) mode, an external device only needs to send a command to the DMA controller after the data is ready, the address and the size of the data are transmitted, and the DMA controller is responsible for directly storing the data from the external device to the system memory, so that the overall throughput capacity of the system is greatly improved. The Zynq 7000 series provides DMA, CDMA, VDMA three DMA IP cores, of which DMA IP cores are most widely used, which provide high bandwidth direct memory access between memory and AXI4-Stream target peripherals. Because the DMA IP core provided by the Xilinx integrates the PS-to-PL channel and the PL-to-PS channel, the flexibility is insufficient, a user cannot add a custom interface, and special requirements in practical application are difficult to deal with. Therefore, it is of great importance to develop a custom DMA IP core based on AXI bus suitable for Zynq 7000. Disclosure of Invention The invention aims to solve the problem that the DMA IP core under the prior Zynq 7000 has insufficient flexibility and cannot meet special requirements in practical application, and provides an AXI bus-based implementation method of the self-defined DMA IP core. In order to achieve the above purpose, the technical scheme adopted by the invention is as follows: a method for realizing self-defining DMA IP core based on AXI bus includes IP core establishment process from PS channel to PL channel and IP core establishment process from PL channel to PS channel; the IP core establishment process from the PS channel to the PL channel is as follows: s1, creating an IP core with an AXI4 interface, and adding an S00 AXI port, an M00 AXI port and an M_AXIS port; S2, receiving PS end control data through an SOO_AXI port, wherein a write address channel signal in the SOO_AXI port is used as a starting address for receiving the control data, a write data channel signal is used as the received control data, and the address is shifted by a fixed byte after each data reception; analyzing the received control data, sending the analyzed control data information to an MOO_AXI port as a base address and total data length of PS-end high-speed data received by a PL end, wherein the analyzed control data information comprises a 0 th bit data effective signal, a1 st to 32 nd bit data length signal and a 33 rd to 64 th bit data base address signal; S3, receiving high-speed data of a PS end through a MOO_AXI port, wherein a PL end is a host, the PS end is a slave, taking a data base address signal as a read address channel signal of the MOO_AXI port, receiving high-speed data from the read data channel signal, receiving a total length data length signal, calculating an effective mark signal, a signal turning signal and an end mark signal required by a time sequence of an M_AXIS port through a data effective signal, converting the high-speed data, the effective mark signal, the signal turning signal and the end mark signal into a time sequence of M_AXIS, and transmitting the converted data to the PL end through the M_AXIS port; The IP core establishment process from the PL channel to the PS channel is as follows: s4, creating an IP core with an AXI4 interface, and adding an S00 AXI port, an M00 AXI port and an S_AXIS port; S5, receiving PS end control data through an SOO_AXI port, using a write address channel signal in the SOO_AXI port as a starting address for receiving the control data, using the write address channel signal as the received control data, shifting the address of the received control data by a fixed byte after each time of receiving the control data, analyzing the received control data, and sending analyzed control data information to the MOO_AXI port, wherein the analyzed control data information comprises a base address and total data length information required by a PL end for sending PS end high-speed data; S6, receiving PL end high-speed data through the S_AXIS port, wherein the PL end high-speed data comprises a high-speed data signal, an effective mark signal, a signal turning signal and an end mark signal, transmitting the high-speed data to the MOO_AXI port, and transmitting the high-speed data to the PS end at the MOO_AXI port ac