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CN-116052751-B - Test circuit, test method and test system

CN116052751BCN 116052751 BCN116052751 BCN 116052751BCN-116052751-B

Abstract

The application relates to a test circuit, a test method and a test system, and belongs to the field of integrated circuits. The test circuit comprises an oscillation circuit and a counter, wherein the oscillation circuit is used for being connected with a target storage unit circuit in a memory, the oscillation circuit is used for generating an oscillation signal related to the reading capability of the target storage unit circuit, and the counter is used for counting the oscillation cycle number of the oscillation signal in a period of time, and the oscillation cycle number is used for representing the reading capability of the target storage unit circuit. The oscillating circuit is used for being matched with a target storage unit circuit in the memory, so that an oscillating signal related to the reading capability of the target storage unit circuit is generated, and the oscillating period number of the oscillating signal in a period of time (the time can be flexibly set according to the test requirement) is counted, so that the reading capability of the target storage unit circuit is detected.

Inventors

  • HUANG RUIFENG
  • YANG CHANGKAI

Assignees

  • 海光信息技术股份有限公司

Dates

Publication Date
20260512
Application Date
20221222

Claims (13)

  1. 1. A test circuit, comprising: An oscillating circuit for connecting with a target memory cell circuit in a memory, generating an oscillating signal related to a read capability of the target memory cell circuit; a counter for counting a number of oscillation cycles of the oscillation signal over a period of time, the number of oscillation cycles being indicative of a read capability of the target memory cell circuit; Wherein the oscillating circuit includes: the output end of the first logic device is connected with the word lines of the target memory cell circuit, the first logic device is used for outputting own input signals in an opposite phase, and the number of the first logic devices is the same as that of the word lines in the target memory cell circuit; The output end of the second logic device is connected with the precharge control line of the target memory cell circuit, and the second logic device is used for outputting own input signals in an opposite phase; And the input end of the third logic device is connected with one bit line of the target memory cell circuit, the output end of the third logic device is also respectively connected with the first logic device and the second logic device, and the third logic device is used for outputting own input signals in an opposite phase.
  2. 2. The test circuit of claim 1, wherein the target memory cell circuit comprises M memory cells in series, the M memory cells being controlled by M word lines, M being an integer greater than or equal to 2, the test circuit further comprising: The control module is used for generating word line control signals; and the decoder is connected with the control module and the M word lines, and is used for decoding the word line control signals and enabling the corresponding word lines according to decoding results so that the test circuit can test the whole reading capacity of the M memory cells or the reading capacity of any one of the M memory cells.
  3. 3. The test circuit of claim 2, wherein the control module comprises a count controller connected to the oscillating circuit, the count controller is configured to count the number of oscillation cycles of the oscillating signal, and generate word line control signals according to the count result, and word line control signals generated by different count results are different, so that the test circuit can realize the test of the overall read capability of the M memory cells.
  4. 4. The test circuit of claim 2, wherein the control module comprises a register for generating a word line control signal based on a configuration parameter to cause the test circuit to perform a test of the read capability of any one of the M memory cells.
  5. 5. The test circuit of claim 2, wherein the target memory cell circuit comprises N columns of M memory cells connected in series, the N memory cells connected in parallel in the same row are controlled by the same WL, the M memory cells connected in series in the same column are controlled one by M word lines, and N is an integer greater than or equal to 2; the number of the oscillating circuits is N, and each oscillating circuit is used for being connected with M storage units connected in series with the same column; the selector is connected with each oscillating circuit, and the selector is used for selecting one oscillating signal from N oscillating signals and transmitting the one oscillating signal to the counter so that the test circuit can realize the test of the whole reading capability of any one of N columns of memory cells or the test of the reading capability of any one of N columns of memory cells.
  6. 6. The test circuit of any of claims 1-5, wherein the second logic device is of the same type as the third logic device.
  7. 7. The test circuit of any of claims 1-5, wherein the second logic device, the third logic device comprises an inverter, a nor gate, or a nand gate.
  8. 8. The test circuit of any one of claims 1-5, wherein the first logic device comprises an inverter and a switch; The input end of the inverter is connected with the output end of the third logic device, the output end of the inverter is connected with the signal input end of the switch, the signal output end of the switch is connected with the word line of the target memory cell circuit, and the control end of the switch is used for receiving a word line control signal.
  9. 9. The test circuit of any one of claims 1-5, wherein the first logic device comprises an inverter and a nor gate; The first signal input end of the NOR gate is connected with the signal output end of the third logic device, the output end of the NOR gate is connected with the word line of the target storage unit circuit, the output end of the inverter is connected with the second signal input end of the NOR gate, and the input end of the inverter is used for receiving a word line control signal.
  10. 10. A test system comprising a memory and a test circuit as claimed in any one of claims 1 to 9 for testing the read capability of the memory.
  11. 11. A method of testing, comprising: the method comprises the following steps: Generating an oscillating signal related to a read capability of a target memory cell circuit in a memory using an oscillating circuit; counting the number of oscillation cycles of the oscillation signal in a period of time, wherein the number of oscillation cycles is used for representing the reading capability of the target memory cell circuit; Wherein the oscillating circuit includes: the output end of the first logic device is connected with the word lines of the target memory cell circuit, the first logic device is used for outputting own input signals in an opposite phase, and the number of the first logic devices is the same as that of the word lines in the target memory cell circuit; The output end of the second logic device is connected with the precharge control line of the target memory cell circuit, and the second logic device is used for outputting own input signals in an opposite phase; And the input end of the third logic device is connected with one bit line of the target memory cell circuit, the output end of the third logic device is also respectively connected with the first logic device and the second logic device, and the third logic device is used for outputting own input signals in an opposite phase.
  12. 12. The method of claim 11, wherein the target memory cell circuit includes M memory cells in series, the M memory cells being controlled by M word lines, M being an integer greater than or equal to 2, the method further comprising: Generating a word line control signal, and controlling corresponding word line enabling based on the word line control signal to realize the test of the whole reading capability of the M memory cells or the test of the reading capability of any one of the M memory cells.
  13. 13. The test method of claim 12, wherein the target memory cell circuit comprises N columns of M memory cells connected in series, the N memory cells connected in parallel in the same row are controlled by the same WL, the number of the oscillating circuits is N, each of the oscillating circuits is used for connecting the M memory cells connected in series in the same column, N is an integer greater than or equal to 2, and before counting the number of oscillation cycles of the oscillating signal in a period of time, the method further comprises: One oscillation signal is selected and outputted from the N oscillation signals so as to realize the test of the whole reading capability of any one of the N columns of the memory cells or the test of the reading capability of any one of the N columns of the memory cells.

Description

Test circuit, test method and test system Technical Field The application belongs to the field of integrated circuits, and particularly relates to a test circuit, a test method and a test system. Background In the memory production process, the read-write capability of the memory cell (cell) drifts due to the process and the process drift. The MOS tube in the memory unit is designed in advance by a process manufacturer, and the size, the position, the connection with metal wires and the like of the MOS tube are fixed and can not be changed at will, and the MOS tube is different from the common MOS tube and can be placed and connected at will, so that the read-write capability of the memory unit of the memory is difficult to detect after the memory unit is made of silicon. Disclosure of Invention In view of the above, the present application is directed to a testing circuit, a testing method and a testing system for rapidly detecting the reading capability of a memory cell during the chip generation process. Embodiments of the present application are implemented as follows: In a first aspect, an embodiment of the present application provides a test circuit, including an oscillation circuit and a counter, where the oscillation circuit is configured to be connected to a target memory cell circuit in a memory, the oscillation circuit is configured to generate an oscillation signal related to a read capability of the target memory cell circuit, and the counter is configured to count an oscillation cycle number of the oscillation signal over a period of time, where the oscillation cycle number is configured to characterize the read capability of the target memory cell circuit. In the embodiment of the application, the oscillating circuit is utilized to be matched with the target storage unit circuit in the memory, so that the oscillating signal related to the reading capability of the target storage unit circuit is generated, and the oscillating period number of the oscillating signal is counted within a period of time (the time can be flexibly set according to the test requirement), thereby realizing the detection of the reading capability of the target storage unit circuit. With reference to one possible implementation manner of the first aspect, the target memory cell circuit includes M memory cells connected in series, where M memory cells are controlled by M word lines, and M is an integer greater than or equal to 2, and the test circuit further includes a control module and a decoder, where the control module is configured to generate a word line control signal, and the decoder is connected to the control module and the M word lines, and is configured to decode the word line control signal, and enable the corresponding word line according to a decoding result, so that the test circuit performs a test on an overall read capability of the M memory cells, or a test on a read capability of any memory cell of the M memory cells. In the embodiment of the application, the control module and the decoder are additionally arranged, so that the test circuit can realize the test of the whole reading capability of M storage units or the test of the reading capability of any storage unit in the M storage units, thereby meeting different test requirements. With reference to a possible implementation manner of the first aspect, the control module includes a count controller connected to the oscillation circuit, where the count controller is configured to count an oscillation cycle number of the oscillation signal, generate a word line control signal according to a count result, and generate different word line control signals according to different count results, so that the test circuit realizes a test of an overall reading capability of the M memory cells. In the embodiment of the application, the counting controller is adopted to count the oscillation period number of the oscillation signals, and the word line control signals are generated according to the counting results (the word line control signals generated by different counting results are different), so that the test of the integral reading capability of M storage units can be realized without software logic configuration, and the labor cost of software development is saved. With reference to a possible implementation manner of the embodiment of the first aspect, the control module includes a register, where the register is configured to generate a word line control signal according to a configuration parameter, so that the test circuit implements a test of a read capability of any one of the M memory cells. In the embodiment of the application, the required generated word line control signal can be generated only by configuring the configuration parameters of the register, so that the test circuit can test the reading capability of any one of M memory units, and compared with the mode of software logic configuration, the method has the advantage that the labor