CN-116053279-B - Semiconductor device and manufacturing method thereof

CN116053279BCN 116053279 BCN116053279 BCN 116053279BCN-116053279-B

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for simplifying the manufacturing process of a source region and a drain region of a gate-around transistor positioned below in a CFET device, so as to reduce the integration difficulty of the CFET device. The semiconductor device includes a first semiconductor substrate, a junction-less gate-all-around transistor, and an enhancement-mode gate-all-around transistor. The junction-free type gate-all-around transistor is formed on the first semiconductor substrate. The enhancement mode gate-all-around transistor is formed above the non-junction gate-all-around transistor and is spaced apart from the non-junction gate-all-around transistor. The enhancement mode gate-all-around transistor is of opposite conductivity type to the non-junction gate-all-around transistor. The manufacturing method of the semiconductor device is used for manufacturing the semiconductor device.

Inventors

LI YONGLIANG
JIA XIAOFENG
ZHAO FEI

Assignees

中国科学院微电子研究所

Dates

Publication Date: 20260505
Application Date: 20221230

Claims (15)

1. A semiconductor device includes a first semiconductor substrate, A junction-free gate-all-around transistor formed on the first semiconductor substrate; An enhancement-type junction gate-all-around transistor formed above and spaced apart from the non-junction gate-all-around transistor, the enhancement-type junction gate-all-around transistor being of opposite conductivity type to the non-junction gate-all-around transistor; the channel region of the enhanced junction type gate-all-around transistor comprises a first material part and a second material part surrounding the periphery of the first material part, the material of the second material part is different from that of the first material part, and the material of the first material part is the same as that of the channel region of the junction-free gate-all-around transistor.
2. The semiconductor device of claim 1, wherein the junction-less gate-all-around transistor comprises a channel region of a different material than a channel region of the enhancement-mode gate-all-around transistor.
3. The semiconductor device according to claim 1, wherein in the case where the conductivity type of the enhancement mode junction gate-all-around transistor is a P type, the material of the first material portion is silicon and the material of the second material portion is a high mobility channel material, or, In the case where the conductivity type of the enhancement mode junction gate-all-around transistor is N-type, the material of the first material portion is a high mobility channel material, and the material of the second material portion is silicon.
4. The semiconductor device of claim 1, wherein the junction-less gate-all-around transistor comprises a channel region having a different crystal orientation than a channel region comprised by the enhancement-mode gate-all-around transistor.
5. The semiconductor device according to claim 4, wherein a channel region included in one of the junction-less gate-all-around transistor and the enhancement-mode gate-all-around transistor, which is P-type in conductivity type, has a [110] crystal orientation.
6. The semiconductor device according to claim 4, wherein in a case where a material of a channel region included in one of the non-junction type gate-all-around transistor and the enhancement type gate-all-around transistor having a conductivity type of N is silicon, a crystal orientation of the channel region included in one of the non-junction type gate-all-around transistor and the enhancement type gate-all-around transistor having a conductivity type of N is a [100] crystal orientation, or, In the case where the material of the channel region included in one of the non-junction type gate-all-around transistor and the enhancement-junction type gate-all-around transistor whose conductivity type is N type is a high mobility channel material, the crystal orientation of the channel region included in one of the non-junction type gate-all-around transistor and the enhancement-junction type gate-all-around transistor whose conductivity type is N type is a [111] crystal orientation.
7. The semiconductor device of claim 1, wherein the junction-less gate-all-around transistor comprises a channel region having a width greater than a width of the channel region comprised by the enhancement-mode gate-all-around transistor and/or, The junction-less gate-all-around transistor includes a channel region having a thickness greater than a thickness of the channel region included in the enhancement-mode gate-all-around transistor.
8. A method of manufacturing a semiconductor device, comprising: Providing a first semiconductor substrate; the method comprises the steps of forming a non-junction type ring gate transistor on a first semiconductor substrate, forming an enhanced junction type ring gate transistor which is arranged above the non-junction type ring gate transistor at intervals, wherein the enhanced junction type ring gate transistor is opposite to the non-junction type ring gate transistor in conduction type, a channel region of the enhanced junction type ring gate transistor comprises a first material part and a second material part which surrounds the periphery of the first material part, the material of the second material part is different from the material of the first material part, and the material of the first material part is the same as the material of a channel region of the non-junction type ring gate transistor.
9. The method of manufacturing a semiconductor device according to claim 8, wherein forming a junction-free gate around transistor on the first semiconductor substrate and forming an enhancement-mode junction-free gate around transistor above the junction-free gate around transistor at a distance from the junction-free gate around transistor comprises: The bonding structure comprises the first semiconductor substrate, at least one first semiconductor layer, a bonding layer and at least one second semiconductor layer, wherein the at least one first semiconductor layer, the bonding layer and the at least one second semiconductor layer are sequentially stacked on the first semiconductor substrate along the thickness direction of the first semiconductor substrate; Patterning at least the at least one first semiconductor layer, the bonding layer, and the at least one second semiconductor layer to form a fin structure on the first semiconductor substrate; the junction-free gate-all-around transistor is formed based on the at least one first semiconductor layer after patterning, and the enhancement-mode gate-all-around transistor is formed based on the at least one second semiconductor layer after patterning.
10. The method of manufacturing a semiconductor device according to claim 9, wherein in the case where the channel region included in the junction-free gate-around transistor includes at least two layers of nanowires or sheets, the bonding structure includes at least two layers of the first semiconductor layer, the bonding structure further includes at least one layer of a third semiconductor layer, each layer of the third semiconductor layer is located between two adjacent layers of the first semiconductor layer or between an underlying layer of the first semiconductor layer and the first semiconductor substrate, materials of the third semiconductor layer and the first semiconductor layer are different, and/or, In the case that the channel region included in the enhanced junction type gate-all-around transistor comprises at least two layers of nanowires or sheets, the bonding structure comprises at least two layers of second semiconductor layers, the bonding structure further comprises at least one layer of fourth semiconductor layer, each layer of fourth semiconductor layer is located between two adjacent layers of second semiconductor layers or is located on the second semiconductor layer of the top layer, and materials of the fourth semiconductor layer and the second semiconductor layer are different.
11. The method according to claim 9, wherein in the case where the material of the at least one first semiconductor layer contains germanium, the bonding structure further comprises a first strain buffer layer between the first semiconductor substrate and the at least one first semiconductor layer.
12. The method of manufacturing a semiconductor device according to claim 9, wherein the forming a bonding structure comprises: sequentially forming at least one first semiconductor layer and a first bonding sub-layer positioned on the at least one first semiconductor layer along the thickness direction of the first semiconductor substrate; Forming a second semiconductor base including a semiconductor substrate, the at least one second semiconductor layer formed on the semiconductor substrate, and a second bonding sub-layer formed on the at least one second semiconductor layer; bonding the second semiconductor substrate on the first bonding sub-layer by using one side of the second bonding sub-layer, which is away from the semiconductor substrate; And removing at least the semiconductor substrate to obtain the bonding structure, wherein the bonding layer comprises the first bonding sub-layer and the second bonding sub-layer.
13. The method for manufacturing a semiconductor device according to claim 12, wherein in a case where a material of the at least one second semiconductor layer contains germanium, the second semiconductor base further includes a second strain buffer layer between the semiconductor substrate and the at least one second semiconductor layer; the removing at least the semiconductor substrate includes removing the semiconductor substrate and the second strain buffer layer.
14. The method for manufacturing the semiconductor device according to claim 9, wherein the junction-less gate-all-around transistor includes a channel region having a width larger than a width of the channel region included in the enhancement-mode gate-all-around transistor; The patterning of the at least one first semiconductor layer, the bonding layer, and the at least one second semiconductor layer to form a fin structure on the first semiconductor substrate includes: Under the mask action of the first mask layer, at least one layer of second semiconductor layer and the bonding layer are subjected to patterning treatment in sequence to form a first fin part, wherein the first mask layer covers part of the area of the at least one layer of second semiconductor layer; forming a second mask layer at least on two sides of the first fin portion along the width direction; Under the mask action of the first mask layer and the second mask layer, at least patterning the at least one first semiconductor layer to form a second fin portion, wherein the fin structure comprises the second fin portion and the first fin portion; And removing the first mask layer and the second mask layer.
15. The method of manufacturing a semiconductor device according to claim 9, wherein the fin structure includes a first region, a second region, and a third region between the first region and the second region along a length direction of the fin structure; The forming the enhanced junction gate-all-around transistor based on the at least one second semiconductor layer after patterning comprises the following steps: The method comprises the steps of carrying out thinning treatment on a part of at least one second semiconductor layer corresponding to a third area under the mask action of a third mask layer, wherein the third mask layer covers a part of at least one first semiconductor layer corresponding to the third area, and the top height of the third mask layer is larger than the top height of the first semiconductor layer positioned at the top layer and smaller than the bottom height of the second semiconductor layer positioned at the bottom layer; Forming a second material part on the periphery of each layer of the first material part, wherein a channel region included in the enhanced junction type gate-all-around transistor comprises the first material part and the second material part, and the second material part is made of a material different from the first material part; And removing the third mask layer.

Description

Semiconductor device and manufacturing method thereof Technical Field The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor device and a method for manufacturing the same. Background Complementary field effect Transistor devices (CFET) include vertically stacked NMOS (N-Metal-Oxide-Semiconductor) and PMOS (P-Metal-Oxide-Semiconductor) transistors to increase the integration density of CMOS devices. However, the manufacturing process of the existing CFET device is complicated, and the integration difficulty of the CFET device is high. Disclosure of Invention The invention aims to provide a semiconductor device and a manufacturing method thereof, which are used for simplifying the manufacturing process of a source region and a drain region of a gate-all-around transistor positioned below in a CFET device, so as to reduce the integration difficulty of the CFET device. In order to achieve the above object, the present invention provides a semiconductor device including a first semiconductor substrate, a junction-free gate-all-around transistor, and an enhancement-mode gate-all-around transistor. The junction-free type gate-all-around transistor is formed on the first semiconductor substrate. The enhancement mode gate-all-around transistor is formed above the non-junction gate-all-around transistor and is spaced apart from the non-junction gate-all-around transistor. The enhancement mode gate-all-around transistor is of opposite conductivity type to the non-junction gate-all-around transistor. Compared with the prior art, in the semiconductor device provided by the invention, the enhanced junction type gate-all-around transistor is positioned above the junction-free gate-all-around transistor. In addition, the conductivity types of the enhanced junction type gate-all-around transistor are different from those of the non-junction type gate-all-around transistor, so that the enhanced junction type gate-all-around transistor and the non-junction type gate-all-around transistor form a CFET device so as to improve the integration density of the CMOS device. In addition, a transistor located below in the semiconductor device is a junction-free type gate-all-around transistor. Because PN junctions are not included in the junction-free type gate-all-around transistor, impurity doping types of a source region, a drain region and a channel region are the same, in an actual manufacturing process, when a first semiconductor layer for manufacturing the junction-free type gate-all-around transistor is formed on a first semiconductor substrate, at least a part of the first semiconductor layer is doped, the source region, the drain region and the channel region included in the junction-free type gate-all-around transistor can be formed, and therefore the problem that in the prior art, the process complexity is high due to the fact that after fin structures are formed, the source region and the drain region included in the N-type gate-all-around transistor and the P-type gate-all-around transistor are formed respectively is solved, the manufacturing process of the CFET device is simplified, the integration difficulty of the CFET device is reduced, and meanwhile the manufacturing efficiency of the CFET device is improved. Further, the transistor located above in the semiconductor device is an enhancement junction type gate-all-around transistor. Based on the above, compared with the non-junction type gate-all-around transistor, the electrical performance of the enhanced junction type gate-all-around transistor is less affected by the fluctuation of the doping process, and the on-state current of the enhanced junction type gate-all-around transistor is relatively larger, so that the electrical characteristics of the CFET device are improved when the transistor positioned above is the enhanced junction type gate-all-around transistor. The invention provides a manufacturing method of a semiconductor device, which comprises the following steps: a first semiconductor substrate is provided. And forming an enhanced junction type gate-all-around transistor above the junction-less gate-all-around transistor at a distance from the junction-less gate-all-around transistor. The enhancement mode gate-all-around transistor is of opposite conductivity type to the non-junction gate-all-around transistor. Compared with the prior art, the method for manufacturing the semiconductor device has the beneficial effects that the method can refer to the beneficial effect analysis of the semiconductor device, and the description is omitted here. Drawings The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings: Parts (1)