CN-116056444-B - SRAM device and method of forming the same

Abstract

A forming method of the SRAM device comprises the steps of providing a substrate, comprising a first type device region and a second type device region, wherein the first type SRAM device has the largest channel width, the first type device region and the second type device region comprise a transmission gate transistor region, a pull-down transistor region and a pull-up transistor region, laminated structures are formed on the substrate and comprise a first sacrificial layer and a channel layer, the width of each laminated structure in the second type device region is equal to the preset width of a corresponding transistor region in the first type device region, channel width adjustment processing is conducted, in the second type device region, the channel layer with partial width is removed in any one or two transistor regions of the transmission gate transistor region, the pull-down transistor region and the pull-up transistor region, after the channel layer with partial width is removed, the first sacrificial layer is removed, and a grid structure crossing the channel layer is formed after the first sacrificial layer is removed. The invention adopts the same design layout to form a laminated structure, thereby saving the design cost.

Inventors

• WANG NAN

Assignees

• 中芯国际集成电路制造(上海)有限公司
• 中芯国际集成电路制造(北京)有限公司

Dates

Publication Date

20260505

Application Date

20211021

Claims (20)

1. 1. An SRAM device, comprising: A base including a substrate and a plurality of bottom fin portions protruding from the substrate and extending in a first direction, the base including a first type device region for forming a first type SRAM device having a maximum channel width and a second type device region for forming a second type SRAM device, each of the first and second type device regions including a plurality of memory cell regions including first and second sub-cell regions adjacent and centrally symmetric, each of the first and second sub-cell regions including a pass gate transistor region, a pull-down transistor region, and a pull-up transistor region, the bottom fin portions of the same transistor region in the first and second type device regions having equal widths; A channel layer structure suspended above the bottom fin, the channel layer structure including one or more channel layers disposed at intervals along a longitudinal direction, the channel layer structure extending along the first direction, in the first device region, a sidewall of the channel layer along a second direction being flush with a sidewall of the bottom fin of the corresponding transistor region in the longitudinal direction, in the second device region, in any one or both of the pass gate transistor region, the pull-down transistor region, and the pull-up transistor region, a sidewall of the channel layer being recessed inward with respect to a bottom fin sidewall of the corresponding transistor region along the second direction, the second direction being perpendicular to the first direction; And the gate structure is positioned on the substrate and spans a plurality of channel layer structures along the second direction, and comprises a gate dielectric layer surrounding and covering the channel layer and a gate electrode layer surrounding and covering the gate dielectric layer.
2. 2. The SRAM device of claim 1, wherein in the first type device region, a width of a bottom fin in the pull-up transistor region is a first width, and widths of bottom fins in the pull-down transistor region and the pass-gate transistor region are equal and a second width, the second width being twice the first width, in the second direction.
3. 3. The SRAM device of claim 1 or 2, wherein the second type device region comprises one or both of a first sub-type device region for forming a first sub-type SRAM device and a second sub-type device region for forming a second sub-type SRAM device, wherein an alpha ratio of the first sub-type SRAM device is greater than an alpha ratio of the first type SRAM device, and a beta ratio of the second sub-type SRAM device is greater than a beta ratio of the first type SRAM device; In the pull-down transistor region and the pass-gate transistor region of the first sub-device region, sidewalls of the channel layer are recessed inwardly with respect to bottom fin sidewalls of the respective transistor regions along the second direction; In the pass-gate transistor region of the second sub-device region, sidewalls of the channel layer are recessed inwardly with respect to bottom fin sidewalls of the respective transistor region in the second direction.
4. 4. The SRAM device of claim 3, wherein in the first type of SRAM device, a channel width ratio in the pull-up transistor region, the pass-gate transistor region, and the pull-down transistor region is 1:2:2; In the first sub-class SRAM device, the channel width ratio in the pull-up transistor region, pass-gate transistor region, and pull-down transistor region is 1:1:1.
5. 5. The SRAM device of claim 4, wherein in the first type device region, a width of the bottom fin in the pull-up transistor region is a first width, and widths of the bottom fins in the pull-down transistor region and the pass-gate transistor region are equal and a second width, the second width being twice the first width, in the second direction; The channel layer has a first width in the pull-down transistor region and the pass-gate transistor region of the first sub-device region.
6. 6. The SRAM device of claim 3, wherein in the first type of SRAM device, a channel width ratio in the pull-up transistor region, the pass-gate transistor region, and the pull-down transistor region is 1:2:2; in the second sub-class SRAM device, the channel width ratio in the pull-up transistor region, pass-gate transistor region, and pull-down transistor region is 1:1:2.
7. 7. The SRAM device of claim 6, wherein in the first type device region, a width of the bottom fin in the pull-up transistor region is a first width, and widths of the bottom fins in the pull-down transistor region and the pass-gate transistor region are equal and a second width, the second width being twice the first width, in the second direction; In the pass gate transistor region of the second sub-device region, the width of the channel layer is a first width.
8. 8. The SRAM device of claim 1, in which a material of the channel layer comprises silicon, germanium, silicon germanium, or a III-V semiconductor material.
9. 9. The SRAM device of claim 1, wherein a material of the gate dielectric layer comprises one or more of HfO 2 、ZrO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al 2 O 3 、SiO 2 and La 2 O 3 , and a material of the gate electrode layer comprises one or more of TiN, taN, ta, ti, tiAl, W, AL, tiSiN and TiAlC.
10. 10. A method of forming an SRAM device, comprising: Providing a substrate comprising a first type device region for forming a first type SRAM device and a second type device region for forming a second type SRAM device, the first type SRAM device having a maximum channel width, the first type device region and the second type device region each comprising a plurality of memory cell regions, the memory cell regions comprising first and second sub-cell regions that are contiguous and centrally symmetric, the first and second sub-cell regions each comprising a pass gate transistor region, a pull-down transistor region, and a pull-up transistor region, the pass gate transistor region, the pull-down transistor region, and the pull-up transistor region having a stack structure formed on the substrate that extends in a first direction, the stack structure comprising one or more stacked channel stacks comprising a first sacrificial layer and a channel layer on the first sacrificial layer, the stack structure comprising a channel region in the first direction, wherein the stack structure of each transistor region in the first type device region has a corresponding preset width, and the stack structure of each transistor region in the second type device region has a width that is equal to the corresponding transistor region in the preset width in the second type region; performing channel width adjustment processing, wherein in the second type device region, the channel layer with partial width is removed in a second direction in any one or two transistor regions of the transmission gate transistor region, the pull-down transistor region and the pull-up transistor region, and the second direction is perpendicular to the first direction; Removing the first sacrificial layer in the channel region after removing the channel layer with partial width in the channel region; and after the first sacrificial layer in the channel region is removed, forming a gate structure crossing the channel layer in the channel region, wherein the gate structure comprises a gate dielectric layer surrounding and covering the channel layer and a gate electrode layer surrounding and covering the gate dielectric layer.
11. 11. The method of forming an SRAM device of claim 10, wherein in the step of providing a substrate, in the first type device region, a width of the stacked structure in the pull-up transistor region is a first width, and a width of the stacked structure in the pull-down transistor region and the pass-gate transistor region is equal and is a second width, the second width being twice the first width, in the second direction.
12. 12. The method of forming an SRAM device of claim 10 or 11, wherein in the step of providing a substrate, the second type device region comprises a first sub-type device region for forming a first sub-type SRAM device, the first sub-type SRAM device having an a-ratio that is greater than an a-ratio of the first type SRAM device; The channel width adjustment process includes removing a portion of the channel layer of the channel region width in the second direction in a pull-down transistor region and a pass-gate transistor region of the first sub-device region.
13. 13. The method of forming an SRAM device of claim 12, wherein in the step of providing a substrate, in the first type device region, a width of the stacked structure in the pull-up transistor region is a first width, and a width of the stacked structure in the pull-down transistor region and the pass-gate transistor region is equal and is a second width, the second width being twice the first width, along the second direction; After the channel width adjustment process, the width of the remaining channel layer in the channel region is a first width in the pull-down transistor region and the pass-gate transistor region.
14. 14. The method of forming an SRAM device of claim 12, wherein removing a portion of the channel layer of the channel region in the second direction in the pull-down transistor region and the pass-gate transistor region of the first sub-device region comprises forming a first mask layer in the first sub-device region that covers the pull-up transistor region; After the first mask layer is formed, the channel layer in the channel region is etched in the pull-down transistor region and the pass-gate transistor region of the first sub-device region along the second direction.
15. 15. The method of forming an SRAM device of claim 10, wherein in the step of providing a substrate, the second type device region comprises a second sub-type device region for forming a second sub-type SRAM device, the second sub-type SRAM device having a beta ratio greater than a beta ratio of the first type SRAM device; The channel width adjustment process includes removing a portion of the channel layer of the channel region width in the transfer gate transistor region of the second sub-device region along the second direction.
16. 16. The method of forming an SRAM device of claim 15, wherein in the step of providing a substrate, in the first type device region, a width of the stacked structure in the pull-up transistor region is a first width, and a width of the stacked structure in the pull-down transistor region and the pass-gate transistor region is equal and is a second width, the second width being twice the first width, along the second direction; after the channel width adjustment process, in the pass gate transistor region, a width of a remaining channel layer in the channel region is a first width.
17. 17. The method of forming an SRAM device of claim 15, wherein in the pass gate transistor region of the second sub-class device region, removing a portion of the channel layer of the channel region along the second direction comprises forming a second mask layer in the second sub-class device region covering the pull-up transistor region and the pull-down transistor region; and after the second mask layer is formed, etching the channel layer in the channel region along the second direction in a transmission gate transistor region of the second sub-type device region.
18. 18. The method of forming an SRAM device of claim 10, wherein prior to performing said channel width adjustment process, said method further comprises forming a dummy gate structure across said stack structure, said dummy gate structure covering sidewalls and a top of said stack structure of said channel region; Forming an interlayer dielectric layer covering the side wall of the pseudo gate structure, wherein the interlayer dielectric layer exposes out of the top of the pseudo gate structure; Removing the pseudo gate structure to form a gate opening surrounded by the interlayer dielectric layer, wherein the gate opening exposes the channel layer; removing a portion of the width of the channel layer through the gate opening; Removing the first sacrificial layer in the channel region through the gate opening after removing the channel layer with partial width in the channel region; And after the first sacrificial layer is removed, forming the gate structure in the gate opening.
19. 19. The method of forming an SRAM device of claim 10, wherein after performing said channel width adjustment process, before removing said first sacrificial layer in said channel region, further comprising forming a dummy gate structure across said stack structure, said dummy gate structure covering sidewalls and a top of said stack structure of said channel region; Forming an interlayer dielectric layer covering the side wall of the pseudo gate structure, wherein the interlayer dielectric layer exposes out of the top of the pseudo gate structure; removing the pseudo gate structure to form a gate opening surrounded by the interlayer dielectric layer, wherein the gate opening exposes the first sacrificial layer; removing the first sacrificial layer in the channel region through the gate opening; And after the first sacrificial layer is removed, forming the gate structure in the gate opening.
20. 20. The method of forming an SRAM device of claim 10, wherein in the step of providing the substrate, the stack structure is further formed with a second sacrificial layer thereon covering a top of the stack structure; The step of removing the first sacrificial layer in the channel region further comprises removing the second sacrificial layer of the channel region.

Description

SRAM device and method of forming the same Technical Field The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to an SRAM device and a forming method thereof. Background With the continued development of digital integrated circuits, integrated memory on chip has become an important component in digital systems. SRAM (Static Random Access Memory ) is an integral part of on-chip memory because of its low power consumption and high speed. The SRAM can store data only by supplying power to the SRAM, and the SRAM does not need to be refreshed continuously. The reliability of SRAM is critical to ensure stable and safe operation for electrical applications, and at present, the manufacturing process and the reliability verification process of SRAM are improved. Disclosure of Invention The embodiment of the invention solves the problem of providing an SRAM device and a forming method thereof, which saves design cost, simplifies verification flow and improves verification efficiency. In order to solve the problems, the embodiment of the invention provides an SRAM device, which comprises a substrate and a plurality of bottom fin parts protruding from the substrate and extending along a first direction, wherein the substrate comprises a first type device area used for forming a first type SRAM device and a second type device area used for forming a second type SRAM device, the first type SRAM device has a maximum channel width, the first type device area and the second type device area comprise a plurality of storage unit areas, each storage unit area comprises a first subunit area and a second subunit area which are adjacent and are symmetrical in center, each first subunit area and each second subunit area comprises a transmission gate transistor area, a pull-down transistor area and a pull-up transistor area, and the bottom fin parts of the same transistor area in the first type device area and the second type device area have the same width; a channel layer structure suspended above the bottom fin, the channel layer structure including one or more channel layers spaced apart in a longitudinal direction, the channel layer structure extending in the first direction, in the first device region, sidewalls of the channel layer in a second direction being longitudinally flush with sidewalls of the bottom fin of the corresponding transistor region, in the second device region, in either or both of the pass gate transistor region, the pull-down transistor region, and the pull-up transistor region, sidewalls of the channel layer being recessed inwardly with respect to sidewalls of the bottom fin of the corresponding transistor region in the second direction, the second direction being perpendicular to the first direction, a gate structure on the substrate and crossing the plurality of channel layer structures in the second direction, the gate structure including a gate dielectric layer surrounding and covering the channel layer, and a gate electrode layer surrounding and covering the gate dielectric layer. Correspondingly, the embodiment of the invention also provides a forming method of the SRAM device, which comprises the steps of providing a substrate, comprising a first type device region used for forming the first type SRAM device and a second type device region used for forming the second type SRAM device, wherein the first type device region and the second type device region comprise a plurality of storage unit regions, each storage unit region comprises a first subunit region and a second subunit region which are adjacent and are symmetrical in center, each first subunit region and each second subunit region comprises a transmission gate transistor region, a pull-down transistor region and a pull-up transistor region, a laminated structure extending along a first direction is formed on the substrate of the transmission gate transistor region, the pull-down transistor region and the pull-up transistor region, each laminated structure comprises one or more stacked channel laminates, each channel laminate comprises a first sacrificial layer and a channel layer positioned on the first sacrificial layer, each laminated structure comprises a channel region along the first direction, each transistor region in the first direction comprises a preset width, each transistor region in each laminated structure in the first type device region corresponds to the first sacrificial layer, each channel laminate region in the first direction is removed, each channel laminate is removed in the first direction, and each channel laminate is removed in the first direction, and forming a gate structure crossing the channel layer in the channel region, wherein the gate structure comprises a gate dielectric layer surrounding and covering the channel layer and a gate electrode layer surrounding and covering the gate dielectric layer. Compared with the prior art, the technical scheme of the embodi