CN-116056447-B - Semiconductor structure and forming method thereof

Abstract

The present invention provides a semiconductor structure and a method of forming the same, the semiconductor structure comprises a substrate, a trench, a first conductive layer, a second conductive layer, a third conductive layer, source and drain regions, bit line contacts and storage node contacts. The groove is arranged in the substrate. The first conductive layer is disposed in the trench. The second conductive layer is disposed on the top surface of the first conductive layer. The third conductive layer is disposed on the top surface of the first conductive layer and electrically connected to the second conductive layer. The source electrode region and the drain electrode region are arranged in the substrate and are arranged on the opposite sides of the first conductive layer. A bit line contact is disposed on one of the source region and the drain region, and a storage node contact is disposed on the other of the source region and the drain region.

Inventors

• TANAKA YASUNORI
• ZHANG WEIZHE

Assignees

• 华邦电子股份有限公司

Dates

Publication Date

20260505

Application Date

20211028

Claims (10)

1. 1. A semiconductor structure, comprising: A substrate; a groove arranged in the substrate; a first conductive layer disposed in the trench; A second conductive layer disposed on a top surface of the first conductive layer; a third conductive layer disposed on the top surface of the first conductive layer and electrically connected to the second conductive layer; a source region and a drain region disposed in the substrate and on opposite sides of the first conductive layer; a bit line contact disposed on one of the source region and the drain region, and A storage node contact disposed on the other of the source region and the drain region; Wherein the work function of the first conductive layer and the work function of the third conductive layer are larger than those of the second conductive layer, one of the second conductive layer and the third conductive layer with a higher work function is closer to the bit line contact than the other, and A top surface of the third conductive layer is higher than or coplanar with a top surface of the second conductive layer.
2. 2. The semiconductor structure of claim 1, wherein the second conductive layer and the third conductive layer are in contact with opposite sidewalls of the trench, respectively, and the second conductive layer is in contact with the third conductive layer.
3. 3. The semiconductor structure of claim 1, wherein a ratio of a thickness of the first conductive layer to a thickness of the second conductive layer is 1.67-10.
4. 4. The semiconductor structure of claim 1, wherein a ratio of a thickness of the second conductive layer to a thickness of the third conductive layer is 0.5-2.
5. 5. The semiconductor structure of claim 1, further comprising: a first liner layer disposed between the trench and the first conductive layer; A second liner layer disposed between the first conductive layer and the second conductive layer and between the first conductive layer and the third conductive layer; a first dielectric layer disposed on the second conductive layer, and And the second dielectric layer is arranged on the first dielectric layer and the third conductive layer.
6. 6. A method of forming a semiconductor structure, comprising: Forming a trench in a substrate; forming a first conductive layer in the trench; Forming a second conductive layer on the first conductive layer; forming a sacrificial layer on the second conductive layer; partially removing the sacrificial layer; exposing a portion of the second conductive layer by etching the second conductive layer using the remaining portion of the sacrificial layer as an etching mask, and Forming a third conductive layer on the second conductive layer and covering the exposed portion of the second conductive layer; a source region and a drain region disposed in the substrate and on opposite sides of the first conductive layer; a bit line contact disposed on one of the source region and the drain region, and A storage node contact disposed on the other of the source region and the drain region; Wherein the work function of the first conductive layer and the work function of the third conductive layer are larger than those of the second conductive layer, one of the second conductive layer and the third conductive layer with a higher work function is closer to the bit line contact than the other, and A top surface of the third conductive layer is higher than or coplanar with a top surface of the second conductive layer.
7. 7. The method of forming of claim 6, wherein partially removing the sacrificial layer further comprises: forming a photoresist pattern on the sacrificial layer to cover a portion of the sacrificial layer; Performing an implantation process on the uncovered sacrificial layer; the photoresist pattern and the portion of the sacrificial layer are removed to leave the remaining portion of the sacrificial layer on the second conductive layer.
8. 8. The method of claim 6, wherein the remaining portion of the sacrificial layer is used as an etching mask to etch the second conductive layer and remove the remaining portion of the sacrificial layer.
9. 9. The method of claim 6, wherein the thickness of the sacrificial layer is substantially the same as the thickness of the second conductive layer.
10. 10. The method of forming as claimed in claim 6, further comprising: A first dielectric layer is formed on the second conductive layer, and the remaining portions of the first dielectric layer and the second conductive layer are exposed by etching portions of the first dielectric layer and the second conductive layer using the remaining portions of the sacrificial layer as an etching mask.

Description

Semiconductor structure and forming method thereof Technical Field The present invention relates generally to semiconductor structures and methods of forming the same, and more particularly to semiconductor structures having word line structures with different work function materials and methods of forming the same. Background With the trend of miniaturization of semiconductor devices, the size of memory is continuously reduced, and thus, memory devices with embedded word lines (word lines) are being developed to increase the integration level and improve the performance. However, the continuing shrinkage in size increases capacitive coupling between adjacent elements or components of the interconnect structure and/or creates leakage current problems that adversely affect the performance of the memory, and thus there is a need for structures of the memory device and methods of forming the same that seek to address the problems that cause the adverse effects. Disclosure of Invention In view of the above, the present invention improves the electrical characteristics of the semiconductor structure by providing the word line structure with different work function materials and adjusting the positions of the different work function materials in the word line structure to adjust the relative positions of the different work function materials in the semiconductor structure. For example, a material having a low work function is provided at a position where leakage current is to be avoided, and a material having a high work function is provided at a position where on-current is to be raised, so as to simultaneously avoid leakage current and raise on-current. The semiconductor structure comprises a substrate, a groove, a first conductive layer, a second conductive layer, a third conductive layer, a source electrode region, a drain electrode region, a bit line contact and a storage node contact. The groove is arranged in the substrate. The first conductive layer is disposed in the trench. The second conductive layer is disposed on the top surface of the first conductive layer. The third conductive layer is disposed on the top surface of the first conductive layer and electrically connected to the second conductive layer. The source electrode region and the drain electrode region are arranged in the substrate and are arranged on the opposite sides of the first conductive layer. A bit line contact is disposed on one of the source region and the drain region, and a storage node contact is disposed on the other of the source region and the drain region. The method for forming the semiconductor structure comprises the steps of forming a groove in a substrate. A first conductive layer is formed in the trench. Forming a second conductive layer on the first conductive layer. A sacrificial layer is formed on the second conductive layer. The sacrificial layer is partially removed. A portion of the second conductive layer is exposed by etching the second conductive layer using the remaining portion of the sacrificial layer as an etching mask. A third conductive layer is formed on the second conductive layer and covers the exposed portion of the second conductive layer. Drawings Fig. 1 is a schematic circuit layout of a semiconductor structure provided in accordance with some embodiments of the present invention. Fig. 2-8, 9A, 9B, 10A, 10B, 11A, 11B, 12A, 12B, 13A, 13B, 14A, 14B, 15A, 15B, 16A, 16B, 17A, 17B and 18 are schematic cross-sectional views of semiconductor structures formed at various stages provided according to some embodiments of the invention, and fig. 11C is a schematic circuit layout of semiconductor structures provided according to some embodiments of the invention. Fig. 19 is a schematic cross-sectional view of a semiconductor structure provided in accordance with further embodiments of the invention. Reference numerals illustrate: 1,2 semiconductor structure 100 Substrate 101 First doped region 102 Second doped region 110 Isolation structure 111 Gate dielectric layer 120 Etching mask 121 First groove 122 Second groove 130 First liner 140 First conductive layer 141 Second liner 150 Second conductive layer 160 First dielectric layer 161 Sacrificial layer 161A first part 161B second part 162 Photoresist pattern 163 Implantation process 164 Etching process 170 Third conductive layer 180 Second dielectric layer AA active region BC bit line contact BL bit line CC storage node contact D1 first direction D2, second direction P: current path T1 first thickness T2 second thickness T3 third thickness WL word line Detailed Description Fig. 1 is a schematic circuit layout of a semiconductor structure provided in accordance with some embodiments of the present invention. The semiconductor structure includes a substrate 100, an isolation structure 110, an active region (ACTIVE AREA) AA, a bit line (bit line) BL, a Word Line (WL), a storage node contact (storage node contact) CC, and a bit line contact (bit linecontact) BC. I