CN-116068374-B - Wafer test effectiveness control method, device, computer equipment and storage medium

Abstract

The application relates to a method, a device, computer equipment and a storage medium for controlling the effectiveness of wafer test, wherein the method comprises the steps of obtaining wafer test information obtained by performing wafer test on chips on a wafer; comparing the wafer test information with the set test information corresponding to the wafer to obtain a comparison result, judging whether the wafer is dislocated in the wafer test process according to the comparison result, and determining that the test data of the wafer test are valid if the wafer is not dislocated in the wafer test process. When the wafer is subjected to test dislocation in the wafer test process, the wafer can be found out in time, and the detection accuracy is improved.

Inventors

• GUO HUIFANG
• NI JIALE
• XU BINGBING
• ZHANG SHUIHUA

Assignees

• 上海矽睿科技股份有限公司

Dates

Publication Date

20260508

Application Date

20230130

Claims (9)

1. 1. A wafer test effectiveness control method, comprising: acquiring wafer test information obtained by performing wafer test on chips on a wafer; Comparing the wafer test information with set test information corresponding to the wafer to obtain a comparison result, wherein the wafer test information comprises test results of wafer tests of chips at a plurality of designated positions, and the set test information comprises target test results; judging whether the wafer is misplaced in the wafer testing process according to the comparison result; if the wafer is not subjected to test dislocation in the wafer test process, determining that test data of the wafer test are valid; The wafer test information comprises test results of wafer tests of a plurality of chips at second designated positions, wherein the chips at the second designated positions are chips at the secondary edge positions of the wafer, namely, the chips adjacent to the chips at the edge positions on the wafer, the target test results comprise second target test results, and the second target test results are failure of the chips at the second designated positions in no whole row or whole column.
2. 2. The method of claim 1, wherein determining whether the wafer is misaligned during the wafer test based on the comparison result comprises: if the comparison result is that the test result is consistent with the target test result, the wafer is not subjected to test dislocation in the wafer test process; if the comparison result is that the test result is inconsistent with the target test result, the wafer is subjected to test dislocation in the wafer test process.
3. 3. The method of claim 2, wherein the wafer test information comprises test results of wafer tests of a plurality of chips at first designated locations, the chips at the first designated locations being chips determined based on location information of the design of experiment chips, the target test results comprising first target test results, the first target test results being test results determined by circuit design of the design of experiment chips.
4. 4. The method of claim 2, wherein the test result is information characterizing the validity or invalidity of the chip.
5. 5. The method of claim 4, wherein the test result is further used to indicate a chip failure mode when the test result indicates a chip failure.
6. 6. The method of claim 1, wherein the wafer test information comprises a wafer test station diagram, the set test information comprises a preset standard test station diagram, and the determining whether the wafer is misplaced during the wafer test according to the comparison result comprises: If the comparison result shows that the test station information of the chips is inconsistent with the standard station information, the wafer is subjected to test dislocation in the wafer test process; if the comparison result is that the test station information of all the chips is consistent with the standard station information, the wafer is not subjected to test dislocation in the wafer test process.
7. 7. A wafer test effectiveness control device, comprising: The information acquisition module is used for acquiring wafer test information obtained by carrying out wafer test on chips on a wafer; The data comparison module is used for comparing the wafer test information with set test information corresponding to the wafer to obtain a comparison result, wherein the wafer test information comprises test results of wafer tests of chips at a plurality of designated positions, and the set test information comprises target test results; The data analysis module is used for judging whether the wafer is dislocated in the wafer test process according to the comparison result, and if the wafer is not dislocated in the wafer test process, determining that the test data of the wafer test are valid; The wafer test information comprises test results of wafer tests of a plurality of chips at second designated positions, wherein the chips at the second designated positions are chips at the secondary edge positions of the wafer, namely, the chips adjacent to the chips at the edge positions on the wafer, the target test results comprise second target test results, and the second target test results are failure of the chips at the second designated positions in no whole row or whole column.
8. 8. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the steps of the method of any of claims 1 to 6 when the computer program is executed.
9. 9. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 6.

Description

Wafer test effectiveness control method, device, computer equipment and storage medium Technical Field The present application relates to the field of semiconductor technologies, and in particular, to a wafer test validity control method, a wafer test validity control device, a computer device, and a storage medium. Background After wafer batch production, wafer test is usually performed on each chip on the wafer, and in the subsequent packaging process, the effective chips on the wafer are packaged according to the wafer test result, and the failed chips are removed and not packaged. However, in the manufacturing process, new problems are introduced due to external abnormal factors such as people, equipment, environment, etc., so that the validity of the wafer test needs to be ensured. The traditional wafer test effectiveness control method mainly judges through the test yield and the test wafer diagram, cannot eliminate the conditions of error generation, error call and the like of the test wafer diagram in the test process, so that abnormal chip mixed materials tested by the wafer cannot be effectively screened, huge quality influence can be brought, and the defect of low detection accuracy exists. Disclosure of Invention In view of the foregoing, it is desirable to provide a wafer test effectiveness control method, apparatus, computer device, and storage medium that can improve inspection accuracy. A wafer test effectiveness control method comprises the following steps: acquiring wafer test information obtained by performing wafer test on chips on a wafer; comparing the wafer test information with the set test information corresponding to the wafer to obtain a comparison result; judging whether the wafer is misplaced in the wafer testing process according to the comparison result; and if the wafer is not subjected to test dislocation in the wafer test process, determining that the test data of the wafer test are valid. In one embodiment, the wafer test information includes test results of wafer tests of chips at a plurality of designated positions, the set test information includes target test results, and the determining whether the wafer is dislocated in the wafer test process according to the comparison results includes: if the comparison result is that the test result is consistent with the target test result, the wafer is not subjected to test dislocation in the wafer test process; if the comparison result is that the test result is inconsistent with the target test result, the wafer is subjected to test dislocation in the wafer test process. In one embodiment, the wafer test information includes test results of wafer tests of a plurality of chips at first designated positions, where the chips at the first designated positions are chips determined according to position information of the chips designed for experiments, and the target test results include first target test results, which are test results determined by the chips designed for experiments through circuit design. In one embodiment, the wafer test information includes test results of wafer tests of chips at a plurality of second designated positions, the chips at the second designated positions being chips at wafer sub-edge positions, and the target test results include second target test results, the second target test results being failures of the chips at the second designated positions without whole rows or whole columns. In one embodiment, the test results are information that characterizes the validity or invalidity of the chip. In one embodiment, when the test result indicates a chip failure, the test result is also used to indicate a chip failure mode. In one embodiment, the wafer test information includes a wafer test station diagram, the set test information includes a preset standard test station diagram, and the determining whether the wafer is dislocated in the wafer test process according to the comparison result includes: If the comparison result shows that the test station information of the chips is inconsistent with the standard station information, the wafer is subjected to test dislocation in the wafer test process; if the comparison result is that the test station information of all the chips is consistent with the standard station information, the wafer is not subjected to test dislocation in the wafer test process. A wafer test effectiveness control apparatus comprising: The information acquisition module is used for acquiring wafer test information obtained by carrying out wafer test on chips on a wafer; The data comparison module is used for comparing the wafer test information with the set test information corresponding to the wafer to obtain a comparison result; And the data analysis module is used for judging whether the wafer is misplaced in the wafer test process according to the comparison result, and determining that the test data of the wafer test are valid if the wafer is not misplaced in the wafer test