CN-116089355-B - Mapping method of network-on-chip high-speed data acquisition system

CN116089355BCN 116089355 BCN116089355 BCN 116089355BCN-116089355-B

Abstract

The invention discloses a mapping method of a network-on-chip high-speed data acquisition system, which consists of a network-on-chip mapping model and a mapping effect evaluation model. The on-chip network mapping model consists of an encoder and a decoder, wherein the encoder classifies nodes in a data acquisition system into four types of acquisition nodes, storage nodes, transmission nodes and control nodes according to functions, a graph convolution neural network is adopted to carry out graph coding according to the node types and the connection relation among the nodes in a task graph to obtain encoder vectors of all the nodes in the task graph, keys are used as Query vectors, single-head attention operation is carried out on the Query vectors and unmapped node encoding vectors, attention values of the unmapped nodes are used as the probability that the nodes become next mapping nodes, multiple groups of de-sequences of the same problem are obtained in a beam searching mode, the actual communication time delay of each group of de-sequences is used as a mapping result, and the de-sequence with the smallest communication time delay is selected as a final de-sequence. Training the on-chip network mapping model in a reinforcement learning mode by taking the mapping effect evaluation model as a base line. The mapping method of the network-on-chip high-speed data acquisition system constructed by the invention has the advantage that the same type of problem to be mapped can be solved quickly and efficiently by carrying out model training on the same NoC architecture.

Inventors

XU CHUANPEI
WANG YANG
MA XIAN
SHI XIULI
DENG YUNHUI
HU CONG
NIU JUNHAO

Assignees

桂林电子科技大学

Dates

Publication Date: 20260512
Application Date: 20230222

Claims (4)

1. The mapping method of the network-on-chip high-speed data acquisition system is characterized by comprising the following steps of: step 1, inputting a task graph of a high-speed data acquisition system to be mapped, dividing nodes in the task graph into four types of acquisition nodes, storage nodes, transmission nodes and control nodes according to functions of the nodes, and a one-hot encoding is performed, and, the coding results are respectively acquisition nodes [1, 0], transmission nodes [0,1,0 ]: transmission node [0,1, 0], control node [0, 1]; Step 2, using a node category vector and a task graph adjacency matrix to be mapped as inputs of a graph convolution neural network, wherein the graph convolution neural network extracts node information and inter-node structure information in a task graph to encode each node in the task graph, and an encoder outputs { e 0 ,e 1 ,…,e n-1 ,e n }, and the encoding formula is as follows: Wherein the method comprises the steps of A is the adjacency matrix of the graph, I is the identity matrix, The degree matrix of the graph is that the degree refers to the number of edges connected with the designated nodes in the graph, H is the characteristic of each layer of nodes, and for an input layer, H is an initial input X, and sigma is a nonlinear activation function; step 3, the decoder takes the node coding vectors { e 0 ,e 1 ,…,e n-1 ,e n } and the node classification vectors of the task graph as input, takes the node coding vectors as the global information of the task graph, takes the coding vectors of the 3 recently mapped nodes as the local information of the task graph, dynamically selects the coding vectors of two storage nodes from all storage nodes as the key information of the task graph according to the global information and the local information of the task graph, and the selection of the dynamic key nodes is obtained by a single-head attention mechanism with a mask; Step 4, the decoder fuses the global information, the local information and the dynamic key node information of the task graph as Query vectors of an attention mechanism to calculate the matching degree with the coding vectors of the unmapped nodes, and selects the node with high matching degree as the next mapping node to finish mapping; Step 5, adopting a beam searching method to circulate the step 3 and the step 4 to obtain a plurality of groups of mapping solutions M { M 1 ,M 2 ,…,M n }, and selecting the solution which minimizes the delay of the data acquisition system as the final mapping solution I.e., a numerical arrangement from 1 to n, where the index represents a routing node on the fabric and the element represents an IP core in the task graph; Step 6, the mapping effect evaluation model is composed of a fully-connected neural network, and the communication time delay is estimated aiming at the input task graph to be mapped; And 7, taking the actual system communication time delay of the network-on-chip mapping model as L (pi), taking the system communication time delay estimated by the mapping effect evaluation model as a base line b(s), and optimizing the network-on-chip mapping model through gradient descent, wherein the formula is as follows: Wherein L (θ|s) =e pθ(π|s) [ L (pi) ], L ((θ|s) is the desire of the communication delay of the task graph to be mapped; And 8, taking the system communication time delay L (pi) calculated by the on-chip network mapping model solution sequence as an actual value, taking the system communication time delay b(s) estimated by the mapping effect evaluation model as a predicted value, and optimizing the mapping effect evaluation model by taking a Mean Square Error (MSE) as a loss function, wherein the formula is as follows: MSE(L(π),b(s))=(L(π)-b(s)) 2 。
2. the mapping method of network-on-chip high-speed data acquisition system according to claim 1, wherein the nodes in the task graph of the high-speed data acquisition system are classified according to functions in step 1 and step 2 as initial feature vectors of the nodes, and each node of the task graph is encoded through a graph convolution neural network.
3. The mapping method of the network-on-chip high-speed data acquisition system according to claim 1, wherein in the step 3-4, the task graph global information, the task graph local information and the dynamic key node information are introduced into the mapping model decoder as Query vectors to calculate the similarity for the mapping nodes.
4. The mapping method of the network-on-chip high-speed data acquisition system according to claim 1, wherein in the step 5, a beam search mode is used to obtain multiple groups of mapping solutions of the same task graph to be mapped, and the mapping solution which minimizes the delay of the high-speed data acquisition system is selected as a final solution.

Description

Mapping method of network-on-chip high-speed data acquisition system Technical Field The invention relates to the field of network-on-chip high-speed data acquisition systems, in particular to a network-on-chip system mapping method based on node classification of a data acquisition system. Background The data acquisition technology is an indispensable means for monitoring the state of electronic equipment, and along with the development of national economy, the requirements on indexes such as data acquisition speed and the like are higher and higher. However, the data acquisition and the measurement and control system based on the data acquisition and the measurement and control system and the related high-end instrument and equipment are limited by the manufacturing process of a core device, namely an analog-to-digital converter (Analog to Digital Converter, ADC), and the speed of a single analog-to-digital converter cannot be infinitely increased. Therefore, the multi-chip conversion device adopts a Time-alternating ADC (Time-INTERLEAVED ADC, TIADC) sampling technology, which is one of the most feasible methods for improving the sampling rate and ensuring the sampling performance of the system, and can effectively break through the limitation of the conversion rate of the single-chip ADC chip on the sampling rate of the system, thereby realizing higher-speed data acquisition. The current TIADC is based on the traditional bus architecture design, and along with the rapid development of electronic design and manufacturing process, the system on chip based on the bus architecture faces the bottleneck problems of low communication bandwidth, difficult clock synchronization, poor expandability and the like which are difficult to break through, so that the improvement of performance indexes is influenced, and the expansion of the number of ADC chips is limited. The Network on Chip (NoC) introduces a computer Network technology into a Chip design, is a brand new integrated circuit architecture, adopts a packet and route switching technology to replace a traditional bus technology to realize communication, thoroughly breaks the limitation of the traditional bus communication from the architecture, solves the bottleneck and clock problems of the on-Chip communication, greatly increases the communication bandwidth of the on-Chip system, and ensures that the address space of the on-Chip system is not limited by the on-Chip Network structure, thereby improving the expandability of the circuit. The resource nodes of the network-on-chip are designed as functional nodes for data acquisition, storage, transmission and the like, and an on-chip network data acquisition system which is easy to expand, high in sampling rate, low in delay and high in throughput rate is realized by adopting an alternate sampling principle, so that the problems of difficult synchronization, limited communication bandwidth, poor expandability and the like existing in the traditional bus-based time alternate sampling method are solved. The network-on-chip mapping scheme determines the position of each resource node in the NoC topology structure, so that optimization of the mapping algorithm is an important means for realizing the low power consumption and low delay of the NoC. For a network on chip with a smaller scale, a better scheme can be found in a shorter time by using an exhaustive traversal method or a group intelligent evolution method, however, the more the number of the same type of acquisition nodes in a high-speed data acquisition system is, the higher the acquisition rate of the data acquisition system is, and the more the number of the nodes of the data acquisition system is, the time-consuming the exhaustive traversal method or the group intelligent evolution method becomes. With the development of artificial intelligence technology in recent years, the characteristic of deep reinforcement learning of offline training and online decision-making provides a new method for rapidly solving the mapping problem of a network-on-chip high-speed data acquisition system, so that the deep reinforcement learning method is a good choice for solving the NoC mapping problem. Disclosure of Invention Aiming at the mapping problem of a network-on-chip high-speed data acquisition system, the invention provides a mapping method of the network-on-chip high-speed data acquisition system, which is characterized in that nodes in a task graph of the high-speed data acquisition system are classified according to functions, the nodes in the task graph are encoded through a graph convolution neural network, task graph global information, task graph local information and dynamic key node information are introduced into a mapping model decoder as Query vectors to calculate similarity for mapping nodes, a beam searching mode is used for obtaining multiple groups of mapping solutions of the same task graph to be mapped, and the mapping solution which enables th