CN-116110948-B - Two-dimensional multi-bridge channel transistor with self-aligned source-drain doping and preparation method

CN116110948BCN 116110948 BCN116110948 BCN 116110948BCN-116110948-B

Abstract

The invention provides a two-dimensional multi-bridge channel transistor with self-aligned source-drain doping and a preparation method thereof, wherein the two-dimensional multi-bridge channel transistor comprises a substrate and a plurality of channel structures arranged on the substrate, each channel structure in the plurality of channel structures comprises a gate metal layer arranged on the substrate, and a first high-k gate dielectric layer arranged around the first gate metal layer, a low-k gate dielectric layer arranged around the side surface of the first high-k gate dielectric layer, and a two-dimensional semiconductor material layer arranged on the high-k gate dielectric layer and the low-k gate dielectric layer, wherein part of the two-dimensional semiconductor material is subjected to solid source doping source induced phase change into a two-dimensional semi-metal/metal material layer. According to the two-dimensional multi-bridge channel transistor and the preparation method thereof, the source-drain contact resistance is reduced, the low-k side wall process compatible with a two-dimensional semiconductor integrated circuit is realized, the parasitism is reduced, and the speed of the transistor is improved.

Inventors

JIANG JIANFENG
QIU CHENGUANG
PENG LIANMAO

Assignees

北京大学

Dates

Publication Date: 20260508
Application Date: 20230210

Claims (9)

1. A two-dimensional multi-bridge channel transistor with self-aligned source-drain doping, comprising a substrate and a plurality of channel structures disposed on the substrate, each of the plurality of channel structures comprising: a first gate metal layer disposed on the substrate; A first high-k gate dielectric layer disposed around the first gate metal layer; a low-k gate dielectric layer disposed around a side of the first high-k gate dielectric layer; The two-dimensional semiconductor material layer is arranged on the first high-k gate dielectric layer and the low-k gate dielectric layer, wherein active points of atom injection are generated by utilizing surface modification treatment comprising ultra-low power soft plasma bombardment of the two-dimensional semiconductor material layer, and active metal atoms are injected and substitutionally doped into the two-dimensional semiconductor material layer through annealing treatment, so that part of the two-dimensional semiconductor material is subjected to phase change into the two-dimensional semi-metal/metal material layer by a solid source doping source.
2. The two-dimensional multi-bridge channel transistor with self-aligned source-drain doping of claim 1, wherein said low-k gate dielectric layer is formed using a self-aligned process.
3. The two-dimensional multi-bridge channel transistor with self-aligned source-drain doping of claim 1, further comprising a second gate metal layer disposed over the plurality of channel structures, a second high-k gate dielectric layer surrounding the second gate metal layer, sidewalls disposed on both sides of the second gate metal layer and the second high-k gate dielectric layer, and passivation layers disposed on both sides of the sidewalls.
4. A two-dimensional multi-bridge channel transistor with self-aligned source-drain doping according to any of claims 1-3, further comprising a solid source active metal and a conventional metal layer overlaying said two-dimensional semi-metal/metal material layer.
5. The preparation method of the two-dimensional multi-bridge channel transistor with self-aligned source-drain doping is characterized by comprising the following steps: Step 1, providing a substrate; step 2, preparing a sacrificial layer on the substrate; Step 3, preparing a two-dimensional semiconductor material layer on the sacrificial layer; Step 4, preparing a sacrificial layer on the two-dimensional semiconductor material layer; Repeating the preparing steps of the step 3 and the step 4 more than twice; step 5, preparing a dummy gate structure and a side wall structure on the sacrificial layer farthest from the substrate; Step 6, etching part of the sacrificial layer; Step 7, depositing a low-k gate dielectric layer to cover the dummy gate structure and the side wall structure; step 8, etching the low-k gate dielectric layer by taking the side wall structure as self alignment, and carrying out back etching on the low-k gate dielectric layer; Step 9, bombarding the two-dimensional semiconductor material layer by adopting ultra-low power soft plasma so as to carry out surface modification treatment on the two-dimensional semiconductor material layer; step 10, evaporating a solid source active metal layer; step 11, evaporating a conventional metal layer; and step 12, annealing treatment is carried out, so that the two-dimensional semiconductor material layer is subjected to phase change induced by the solid source doping source to obtain the two-dimensional semi-metal/metal material layer.
6. The method of claim 5, wherein the surface modification process comprises bombarding the two-dimensional semiconductor material layer with ultra-low power soft plasma.
7. The method of fabricating a two-dimensional multi-bridge channel transistor with self-aligned source-drain doping according to claim 5, wherein said annealing is performed by rapid annealing at a temperature of from 250 ℃ to 600 ℃ for 2-60 seconds.
8. The method of claim 5, further comprising removing the dummy gate, removing the sacrificial layer, and then growing a high-k gate dielectric layer and a gate metal layer.
9. The method of fabricating a two-dimensional multi-bridge channel transistor with self-aligned source-drain doping of claim 8, wherein said high-k gate dielectric layer and said gate metal layer are grown using an atomic layer deposition process.

Description

Two-dimensional multi-bridge channel transistor with self-aligned source-drain doping and preparation method Technical Field The invention particularly relates to a self-aligned source-drain doped two-dimensional multi-bridge channel transistor and a preparation method thereof, and belongs to the technical field of two-dimensional semiconductors. Background As integrated circuit fabrication processes enter sub-10 nm nodes, conventional approaches to achieving overall performance enhancement of the chip by scaling transistors equally to increase the unit density of the transistors have become increasingly difficult to achieve. The technology of finfets employed in the industry since the 22nm node has approached its physical and engineering limits at the sub-5 nm technology node, requiring innovation in transistor structure. The transistor (MBCFET) structure with multiple channels stacked and fully-surrounding multiple bridge channels is one of the most potential structures after FinFET, and the fully-surrounding gate structure can realize stronger electrostatic control so as to inhibit short channel effect, and the multi-channel stack can greatly improve driving current, thereby reducing transistor gate delay so as to improve speed. The MBCFET structure is also regarded as a technical route to sub-5 nm nodes by the international semiconductor technology route map. The advanced manufacturing companies of semiconductors such as samsung electronics and Intel are also attacking sub-5 nm process nodes based on technology surrounding gate transistors. Two-dimensional semiconductor materials have significant advantages in terms of speed and power consumption due to their intrinsic advantages of ultra-thin bulk and high mobility, which is one of the candidates for MBCFET core channel materials. The combination of the two-dimensional semiconductor material ultrathin body and the surrounding gate structure can maximally improve the gate control capability of the transistor and inhibit short channel effect, so that the transistor is pushed to a smaller technical node. The contact resistance of the two-dimensional semiconductor material is too high due to the fermi pinning effect, and the silicon-based ion implantation mode can not be adopted for reducing the source-drain contact resistance temporarily, so that MBCFET has poor on-state performance even though the multi-channel stack is formed. New contact processes need to be developed to achieve MBC transistor ohmic contacts to increase transistor speed and reduce circuit delay. In order to reduce parasitic capacitance in two dimensions MBCFET to reduce delay and thereby improve circuit performance, a self-aligned process corresponding to new materials needs to be developed to implement the low-k sidewall process in two dimensions MBCFET. The current self-aligned approach of two-dimensional semiconductors is only demonstrated in metal lift-off processes, which is not compatible with advanced node LSI processes. At present, there is no report on realizing a low-k side wall process in two dimensions MBCFET, and in view of the requirement of reducing delay and improving circuit performance, a technical scheme compatible with the low-k side wall process of a two-dimensional semiconductor integrated circuit to reduce parasitic improvement speed is needed. Disclosure of Invention The invention aims to provide a complete self-aligned two-dimensional semiconductor MBCFET structure and a preparation process, realize the conversion of a two-dimensional semiconductor material from a semiconductor phase to a metal phase, reduce the source-drain contact resistance, and obtain a low-k side wall process compatible with a two-dimensional semiconductor integrated circuit so as to reduce parasitism and improve the speed. In order to achieve the above purpose, the present invention adopts the following technical scheme. A two-dimensional multi-bridge channel transistor with self-aligned source-drain doping comprises a substrate and a plurality of channel structures arranged on the substrate, wherein each channel structure of the plurality of channel structures comprises a gate metal layer arranged on the substrate, a first high-k gate dielectric layer arranged around the first gate metal layer, a low-k gate dielectric layer arranged around the side face of the first high-k gate dielectric layer, and a two-dimensional semiconductor material layer arranged on the high-k gate dielectric layer and the low-k gate dielectric layer, wherein part of the two-dimensional semiconductor material is subjected to phase change into a two-dimensional semi-metal/metal material layer by a solid source doping source. The low-k gate dielectric layer is formed by adopting a self-alignment process. The semiconductor device further comprises a second gate metal layer arranged on the plurality of channel structures, a second high-k gate dielectric layer surrounding the second gate metal layer, side walls arrang