CN-116110963-B - Semiconductor device and method for manufacturing the same

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, wherein the semiconductor device comprises a III-V compound semiconductor layer and a source/drain structure. The source/drain structure is disposed on the III-V compound semiconductor layer. The source/drain structure includes a metal layer and a plurality of metal silicide patterns. The metal layer is disposed on the metal silicide patterns, and a portion of the metal layer is disposed between adjacent metal silicide patterns.

Inventors

• YE ZHIDONG

Assignees

• 联华电子股份有限公司

Dates

Publication Date

20260505

Application Date

20211109

Claims (15)

1. 1. A semiconductor device, comprising: a III-V compound semiconductor layer; A source/drain structure disposed on the III-V compound semiconductor layer, wherein the source/drain structure comprises: A plurality of metal silicide patterns, and A metal layer disposed on the plurality of metal silicide patterns, wherein a portion of the metal layer is disposed between adjacent ones of the plurality of metal silicide patterns, A plurality of first N-type semiconductor regions disposed in the III-V compound semiconductor layer, wherein each of the first N-type semiconductor regions is disposed vertically corresponding to one of the plurality of metal silicide patterns, and A plurality of second N-type semiconductor regions disposed in the III-V compound semiconductor layer, wherein the plurality of second N-type semiconductor regions are disposed corresponding to the portion of the metal layer disposed between the plurality of metal silicide patterns in the vertical direction.
2. 2. The semiconductor device of claim 1, wherein the plurality of metal silicide patterns are separated from each other.
3. 3. The semiconductor device of claim 1, wherein a material composition of said metal layer is different from a material composition of each of said metal silicide patterns.
4. 4. The semiconductor device of claim 1, wherein said source/drain structure further comprises a plurality of metal nitride layers, and each of said metal nitride layers is disposed between one of said plurality of metal silicide patterns and said III-V compound semiconductor layer.
5. 5. The semiconductor device according to claim 4, wherein each of the metal nitride layers comprises a nitride of a metal element, and each of the metal silicide patterns comprises a silicide of the metal element.
6. 6. The semiconductor device according to claim 1, wherein the group III-V compound semiconductor layer comprises: III-V compound semiconductor channel layer, and And a III-V compound semiconductor cap layer disposed on the III-V compound semiconductor channel layer, wherein at least a portion of each of the first N-type semiconductor regions is disposed in the III-V compound semiconductor channel layer.
7. 7. The semiconductor device according to claim 1, wherein the group III-V compound semiconductor layer comprises: III-V compound semiconductor channel layer, and And a III-V compound semiconductor cap layer disposed on the III-V compound semiconductor channel layer, wherein at least a portion of each of the first N-type semiconductor regions is disposed in the III-V compound semiconductor cap layer.
8. 8. The semiconductor device of claim 1, wherein each of said first N-type semiconductor region and each of said second N-type semiconductor region comprises an N-type III-V compound semiconductor region resulting from a nitrogen void.
9. 9. A method of fabricating a semiconductor device, comprising: forming a source/drain structure on the III-V compound semiconductor layer, wherein the source/drain structure comprises: A plurality of metal silicide patterns, and A metal layer disposed on the plurality of metal silicide patterns, wherein a portion of the metal layer is disposed between adjacent ones of the plurality of metal silicide patterns, Wherein the method of forming the plurality of metal silicide patterns comprises: Forming a plurality of metal patterns on the III-V compound semiconductor layer; Forming a silicon layer to cover the plurality of metal patterns and the III-V compound semiconductor layer, and Performing an annealing process, wherein at least a portion of each of the metal patterns and a portion of the silicon layer are converted into the metal silicide pattern by the annealing process, The first N-type semiconductor regions and the second N-type semiconductor regions are formed in the III-V compound semiconductor layer through the annealing manufacturing process, each of the first N-type semiconductor regions is arranged corresponding to one of the metal silicide patterns in the vertical direction, and the second N-type semiconductor regions are arranged corresponding to the part of the metal layer arranged between the metal silicide patterns in the vertical direction.
10. 10. The method of claim 9, wherein the plurality of metal patterns are separated from each other and the plurality of metal silicide patterns are separated from each other.
11. 11. The method of claim 9, wherein said III-V compound semiconductor layer comprises nitrogen, a plurality of metal nitride layers are formed by said annealing process, and each of said metal nitride layers is located between one of said plurality of metal silicide patterns and said III-V compound semiconductor layer.
12. 12. The method of claim 11, wherein each of said metal nitride layers comprises a nitride of a metal element in said plurality of metal patterns, and each of said metal silicide patterns comprises a silicide of said metal element.
13. 13. The method of claim 9, wherein each of said first N-type semiconductor region and each of said second N-type semiconductor region comprises an N-type III-V compound semiconductor region resulting from a nitrogen void.
14. 14. The method for manufacturing a semiconductor device according to claim 9, wherein the group III-V compound semiconductor layer comprises: III-V compound semiconductor channel layer, and And a III-V compound semiconductor cap layer disposed on the III-V compound semiconductor channel layer, wherein at least a portion of each of the first N-type semiconductor regions is disposed and at least a portion of each of the second N-type semiconductor regions is formed in the III-V compound semiconductor channel layer.
15. 15. The method for manufacturing a semiconductor device according to claim 9, further comprising: the silicon layer is removed prior to forming the metal layer.

Description

Semiconductor device and method for manufacturing the same Technical Field The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device including a group III-V compound semiconductor layer and a method for manufacturing the same. Background The III-V semiconductor compounds are applicable to the formation of many kinds of integrated circuit devices, such as high power field effect transistors, high frequency transistors or high electron mobility transistors (high electron mobility transistor, HEMTs), due to their semiconductor properties. In a high electron mobility transistor, two semiconductor materials of different band-gaps combine to form a heterojunction (heterojunction) at the junction (junction) to provide a channel for carriers. In recent years, gallium nitride (GaN) series materials are suitable for high-power and high-frequency products due to the characteristics of wide energy gap and high saturation rate. The gallium nitride series high electron mobility transistor generates two-dimensional electron gas (2 DEG) by the piezoelectric effect of the material, and has high electron velocity and density, so that the switching speed can be increased. Therefore, it has been a research direction by those skilled in the relevant art how to further improve the electrical performance of transistors formed with III-V compound materials through design changes to the materials, structures, or/and fabrication methods. Disclosure of Invention The invention provides a semiconductor device and a manufacturing method thereof, wherein a plurality of metal silicide patterns and a metal layer arranged on the metal silicide patterns and partially positioned between the adjacent metal silicide patterns are utilized to form a source/drain structure, so that the contact resistance between the source/drain structure and a III-V compound semiconductor layer is reduced, and the operation performance of the semiconductor device is further improved. An embodiment of the present invention provides a semiconductor device including a III-V compound semiconductor layer and a source/drain structure. The source/drain structure is disposed on the III-V compound semiconductor layer, and the source/drain structure includes a plurality of metal silicide patterns and a metal layer. The metal layer is disposed on the metal silicide patterns, and a portion of the metal layer is disposed between adjacent metal silicide patterns. An embodiment of the invention provides a method for manufacturing a semiconductor device, which comprises the following steps. A source/drain structure is formed on a III-V compound semiconductor layer. The source/drain structure includes a plurality of metal silicide patterns and a metal layer. The metal layer is disposed on the metal silicide patterns, and a portion of the metal layer is disposed between adjacent metal silicide patterns. Drawings Fig. 1 is a schematic view of a semiconductor device according to a first embodiment of the present invention; fig. 2 to 7 are schematic views illustrating a method for fabricating a semiconductor device according to a first embodiment of the present invention, in which FIG. 3 is a schematic view of the situation after FIG. 2; FIG. 4 is a schematic view of the situation after FIG. 3; FIG. 5 is a schematic view of the situation after FIG. 4; FIG. 6 is a schematic view of the situation after FIG. 5; fig. 7 is a schematic view of the situation after fig. 6. Fig. 8 is a schematic view of a semiconductor device according to a second embodiment of the present invention; Fig. 9 is a schematic diagram of a method for fabricating a semiconductor device according to a second embodiment of the present invention; fig. 10 is a schematic view of a semiconductor device according to a third embodiment of the present invention; Fig. 11 is a schematic view of a semiconductor device according to a fourth embodiment of the present invention; fig. 12 is a schematic diagram of a method for fabricating a semiconductor device according to a fourth embodiment of the present invention. Description of the main reference signs 10. Substrate 10B bottom surface 10T upper surface 12. Buffer layer 20 III-V compound semiconductor layer 22 III-V compound semiconductor channel layer 24 III-V compound semiconductor cap layer 32. Metal pattern 34. Metal silicide pattern 36. Metal nitride layer 40. Silicon layer 42. Silicon nitride layer 44. Silicon nitride layer 52 N-type semiconductor region 54 N-type semiconductor region 54' N type semiconductor region 62. Metal layer 64. Metal nitride layer 70. Protective layer 91. Annealing manufacturing process 92. Removing and manufacturing process 93. Annealing manufacturing process 101. Semiconductor device with a semiconductor device having a plurality of semiconductor chips 102. Semiconductor device with a semiconductor device having a plurality of semiconductor chips 103. Semico