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CN-116112010-B - High-precision fractional frequency divider applied to broadband phase-locked loop

CN116112010BCN 116112010 BCN116112010 BCN 116112010BCN-116112010-B

Abstract

The invention discloses a high-precision fractional frequency divider applied to a broadband phase-locked loop, which belongs to the field of digital circuits and comprises a 4/5 dual-mode frequency divider module, a 19bit programmable counter module and a programmable sigma-delta modulator module, wherein the 4/5 dual-mode frequency divider module controls switching of 4/5 frequency dividing ratios according to MC signals generated by the 19bit programmable counter module to pre-divide an output signal of a VCO, the 19bit programmable counter module is connected with a 4/5 dual-mode pre-frequency dividing clock signal, the frequency dividing ratios are controlled by 19bit configuration numbers to generate final frequency dividing signals, and in the programmable sigma-delta modulator module, 32bit fractional configuration inputs Fnum/Fden are modulated by the modulator and converted into a series of output sequences, and the series of output sequences are added with an integer part PLL_N to enter the 19bit programmable counter module to generate randomly-changed instantaneous frequency dividing ratios, and the average value of the instantaneous frequency dividing ratios is the value of the final fractional frequency dividing ratios. The invention can realize high-precision fractional frequency division of 7.5 GHz-15 GHz input signals, can reach 0.047Hz step by step, and simultaneously ensures that a phase-locked loop system has lower fractional spurious.

Inventors

  • SHEN JIAN
  • FAN HAIYU
  • YANG JUNHAO
  • QIN ZHANMING
  • SUN WENJUN

Assignees

  • 中国电子科技集团公司第五十八研究所

Dates

Publication Date
20260512
Application Date
20230209

Claims (6)

  1. 1. The high-precision fractional frequency divider applied to the broadband phase-locked loop is characterized by comprising a 4/5 dual-mode frequency divider module, a 19bit programmable counter module and a programmable sigma-delta modulator module; the 4/5 dual-mode frequency divider module controls the switching of the 4/5 frequency dividing ratio according to the MC signal generated by the 19bit programmable counter module at the rear stage, and pre-frequency divides the output signal of the VCO; The 19bit programmable counter module is connected with a 4/5 dual-mode prescaled clock signal, and the frequency division ratio is controlled through the 19bit configuration number to generate a final frequency division signal; In the programmable sigma-delta modulator module, the 32bit fractional configuration input Fnum/Fden is modulated by the modulator and converted into a series of output sequences, and the output sequences are added with an integer part PLL_N and enter the 19bit programmable counter module to generate random variation instantaneous frequency division ratios, wherein the average value of the instantaneous frequency division ratios is the value of the final fractional frequency division ratio; the 4/5 dual-mode frequency divider module comprises 3 cascaded D triggers of full-differential CML, wherein the first and the second are D triggers embedded with AND gate logic, the VCO is connected with clock CLK ports of the 3D triggers through an output signal finP of the buffer, and the VCO is connected with reverse clock CLKn ports of the 3D triggers through an inverted output signal finN of the buffer; the input of the first D trigger is the AND of ports A and B, the port A is connected with the forward output Q of the third D trigger, and the port B is connected with a control signal MC; The input end A of the second D trigger is connected with the reverse output end QN of the third D trigger, and the input end B is connected with the reverse output end QN of the first D trigger; The output ends Q and QN of the third D trigger are a pair of differential signals Fpre _p and Fpre _n after 4/5 double-mode frequency division; the 19bit programmable counter module comprises a 17bit pulse counter and a 2bit synchronous programmable counter, wherein the 17bit pulse counter consists of 17 ECL2 frequency dividers with setting ends and a counting termination detection circuit; The dual-mode frequency division signal Fpre enters the clock end of the first ECL2 frequency divider, the output end of each subsequent stage is sequentially connected with the clock input end of the next stage from the first stage, the programmable control bits DIV_N <18:2> are sequentially connected with the digital setting ends PI of 17 ECL2 frequency dividers respectively, the reverse output ends QN of the 17 ECL2 frequency dividers are sequentially connected with the input end of the counting termination detection logic circuit for detecting the state of each QN, the output signal LD of the counting termination detection logic circuit is connected with the setting end of the 17 ECL2 frequency dividers and the selection end of two 2-to-1 selectors in the 2-bit synchronous programmable counter; The programmable control bits DIV_N <1> and DIV_N <0> are the same or enter the A1 end of a first 2-to-1 selector, DIV_N <1> enters the A0 end of a second 2-to-1 selector, the outputs of the two 2-to-1 selectors are respectively connected with the data D ends of the two D triggers, the dual-mode frequency dividing signal Fpre is connected with the clock ends of the two D triggers, the output Q end of the second D trigger is connected with the A0 end of the first 2-to-1 selector, the reverse output QN end of the first D trigger and the output Q end of the second D trigger are connected to the A1 end of the second 2-to-1 selector after being phase-connected, and the output Q end of the first D trigger and the output Q end of the second D trigger are phase-connected or MC signal is generated to control the switching of the previous 4/5 frequency dividing.
  2. 2. The high-precision fractional divider for a wideband phase locked loop of claim 1, wherein said D flip-flop embedded in AND gate logic comprises transistors Q1-Q20, resistors R1-R8, wherein, The bases of the triodes Q1 and Q2 are respectively connected with the forward input end A and the reverse input end An, and the bases of the triodes Q3 and Q4 are respectively connected with the forward input end B and the reverse input end Bn; the emitters of the audions Q1 and Q2 are connected with the collector of the audion Q3, and the collector of the audion Q1 is simultaneously connected with the first end of the resistor R1, the base of the resistor Q5, the collector of the resistor Q6 and the base of the resistor Q8; the collector of the triode Q2 is connected with the first end of the resistor R2, the collector of the resistor Q4, the collector of the resistor Q5, the base of the resistor Q6 and the base of the resistor Q7; the emitters of the triodes Q3 and Q4 are connected with the collector of Q11, the emitters of the triodes Q5 and Q6 are connected with the collector of Q12, the collector of the triode Q7 is simultaneously connected with the first end of a resistor R3, the base of Q10, the collector of Q9 and the base of Q17, the collector of the triode Q8 is simultaneously connected with the first end of a resistor R4, the base of Q9, the collector of Q10 and the base of Q18, the emitters of the triodes Q7 and Q8 are simultaneously connected with the collector of Q13, the emitters of the triodes Q9 and Q10 are simultaneously connected with the collector of Q14, the bases of the triodes Q11 and Q14 are simultaneously connected with the positive clock input end CLK, the bases of the triodes Q12 and Q13 are simultaneously connected with the collector of Q15, the emitters of the triodes Q13 and Q14 are simultaneously connected with the collector of Q16, the emitters of the triodes Q17 and Q18 and the second ends of R1-R4 are simultaneously connected with VCC, the emitters of the triode Q17 and Q19 are simultaneously connected with the positive output ends of Q19 and the positive output ends of Q18 and the collector of the triodes and the base of Q8 and the collector of the triodes Q20 and the base of the triodes Q8 and the base of the triodes 20 and Q8 are respectively connected with the positive bias ends of the collector and the collector of Q8 and the collector of the triodes and Q8 and the collector of the collector and Q13.
  3. 3. The high-precision fractional divider for a wideband phase locked loop of claim 1, wherein the ECL2 divider with a set terminal comprises transistors Q21-Q48, resistors R9-R20, NMOS transistors M1-M2 and an inverter, wherein, The bases of the triodes Q21, Q22, Q43, Q44, Q45 and Q46 are connected with bias voltage Vbias; the emitters of the triodes Q43, Q44, Q45 and Q46 are grounded through resistors R17, R18, R19 and R20 respectively; the collector of the triode Q21 is simultaneously connected with the first end of a resistor R9, the base of a Q23 and the base of a Q29, the collector of the triode Q22 is simultaneously connected with the first end of a resistor R10, the base of a Q24 and the base of a Q30, the emitters of the triode Q21 and the triode Q22 are respectively connected with the drains of NMOS transistors M1 and M2 through resistors R15 and R16, the grid of the NMOS transistor M1 is connected with a number signal PI, the grid of the NMOS transistor M2 is connected with a number signal PI, the sources of the NMOS transistors M1 and M2 are grounded, the emitters of the triodes M1 and M2 are uniformly connected with the base of a Q39, the bases of the triode Q23 and the base of the Q24 are simultaneously connected with the base of a Q25, the first end of a resistor R11 and the base of a Q31, the collector of a Q27 are simultaneously connected with the base of a Q28, the first end of a resistor R27, the collector of a Q27 and the base of a Q30, the collectors of the triode Q27 are simultaneously connected with the bases of a Q26 and the base of a Q28, the first end of a Q12 and the bases of a Q32, the emitters of a Q25 and the emitters of the triode Q25 are simultaneously connected with the bases of a Q28, the bases of a Q25 and the bases of a Q25, the bases of a Q25 and the bases of a Q32, the bases of a base of a Q32, the base of a Q25 and a Q32, the base of a Q32, the base of a Q32 and the base of a Q12 and a Q33 and a base of a Q12, the base of a Q33 and a base of a Q33, a Q33 and a base of a Q, the bases of Q38 are connected with a forward clock input signal CLK, the bases of triodes Q36 and Q37 are connected with a reverse clock input signal CLKn, the bases of triodes Q39 and Q41 are connected with a forward setting signal LD, the bases of triodes Q40 and Q42 are connected with a reverse setting signal LDn, the emitters of triodes Q39 and Q40 are connected with the collector of Q43, and the emitters of triodes Q41 and Q42 are connected with the collector of Q44.
  4. 4. The high-precision fractional divider applied to a wideband phase-locked loop as claimed in claim 3, wherein the setting signal PI and the setting control signal LD are used for resetting the setting state of the 17bit pulse counter, the ECL2 frequency divider is a divide-by-two frequency divider when the setting control signal LD is at a low level, the frequency division function is stopped when the setting control signal LD is at a high level, the setting signal PI is input to the input through a level conversion signal, and the output terminal q=pi of the ECL2 frequency divider completes the setting operation.
  5. 5. The high-precision fractional divider of claim 1, wherein the programmable sigma-delta modulator module comprises four identical 32bit accumulators, a clock generator, a delta N operation module and a random number generation module, wherein the 32bit accumulators accumulate inputs, the clock generator controls the order of the sigma-delta modulator, the delta N operation module comprises a delay network for carrying out formula calculation on overflow values C1-C4 of the four 32bit accumulators to generate delta N, and the random number generation module generates random 0 and 1 to increase the randomness of an output sequence of the modulator; the sum of the values of the numerator value PLL_NUM <31:0>, the initial value MASH_SEED <31:0> and the PLL_NUM <31:0> enters the input of a first 32bit accumulator through a selector with 2 selected 1 and is controlled by a control word MASH_SEED_EN, the denominator value PLL_DEN <31:0> is connected with the input of four 32bit accumulators, the clocks CLK 1-4 output by the clock generator enter the four 32bit accumulators respectively and are controlled by a register MASH_ORDER <2:0>, and the ORDER of the modulator can be adjusted; The output of the random number generation module enters the input of four 32bit accumulators which are controlled by a register DITHER_EN, overflow values C1-C4 of the four 32bit accumulators enter the delta N operation module to generate an output sequence and a value obtained by adding integer value PLL_N <18:0> to enter the SUM operation device.
  6. 6. The high-precision fractional divider applied to a broadband phase-locked loop as claimed in claim 5, wherein the random number generation module is composed of 24D triggers, three exclusive-or gates and one NOT gate, the D triggers D0-D23 are sequentially connected to form a ring, the output of the D trigger D23 enters the D trigger D0, the outputs of the D triggers D0, D2 and D3 are respectively and firstly exclusive-nor with the output of the D trigger D23 and then respectively enter the next stage, and the final output sequence is output from the D trigger D23 and enters each accumulator.

Description

High-precision fractional frequency divider applied to broadband phase-locked loop Technical Field The invention relates to the technical field of radio frequency circuits, in particular to a high-precision fractional frequency divider applied to a broadband phase-locked loop. Background Wireless communication technology plays an important role in the communication of information today, and its development is closely related to phase-locked loops, which are also being studied more and more. The phase locked loop provides a local oscillation signal for modulation or demodulation in the wireless transceiver, and may provide a clock signal to digital circuitry. Phase locked loops are critical to the proper operation of the overall transceiver system. The frequency divider is an essential important module in the phase-locked loop, and the quality of the frequency divider determines the performance of the whole phase-locked loop. The phase-locked loop can be divided into integer frequency division and fractional frequency division according to frequency division coefficients. The minimum step length of integer frequency division is an integer multiple of the reference frequency, and the frequency precision is limited by the reference frequency. Fractional division can achieve fractional division ratio with higher frequency accuracy. The way to achieve fractional division is to dynamically switch the instantaneous division ratio, but this can lead to the generation of fractional spurs, which in turn affect the spectral purity of the output signal. A common method of eliminating fractional spurs is the sigma-delta modulation technique. Along with the rapid development of radar, millimeter wave and communication technologies, the related fields have higher and higher requirements on key indexes such as working frequency, phase noise and the like of the fractional frequency divider. Therefore, it is highly desirable to design a fractional divider in a system with a wide frequency range, high accuracy, low phase noise, and low spurious performance. Disclosure of Invention The invention aims to provide a high-precision fractional frequency divider applied to a broadband phase-locked loop so as to solve the problems in the background technology. In order to solve the technical problems, the invention provides a high-precision fractional frequency divider applied to a broadband phase-locked loop, which comprises a 4/5 dual-mode frequency divider module, a 19bit programmable counter module and a programmable sigma-delta modulator module; the 4/5 dual-mode frequency divider module controls the switching of the 4/5 frequency dividing ratio according to the MC signal generated by the 19bit programmable counter module at the rear stage, and pre-frequency divides the output signal of the VCO; The 19bit programmable counter module is connected with a 4/5 dual-mode prescaled clock signal, and the frequency division ratio is controlled through the 19bit configuration number to generate a final frequency division signal; In the programmable sigma-delta modulator block, the 32bit fractional configuration input Fnum/Fden is modulated by the modulator and converted into a series of output sequences which are added to the integer part pll_n into the 19bit programmable counter block, generating randomly varying instantaneous divide ratios, the average of which is the value of the final fractional divide ratio. In one embodiment, the 4/5 dual-mode frequency divider module comprises 3 cascaded D flip-flops of fully differential CML, wherein the first and the second are D flip-flops embedded with AND gate logic, the VCO is connected with the clock CLK port of the 3D flip-flops through the output signal finP of the buffer, and the VCO is connected with the inverted clock CLKn port of the 3D flip-flops through the inverted output signal finN of the buffer; the input of the first D trigger is the AND of ports A and B, the port A is connected with the forward output Q of the third D trigger, and the port B is connected with a control signal MC; The input end A of the second D trigger is connected with the reverse output end QN of the third D trigger, and the input end B is connected with the reverse output end QN of the first D trigger; The input end D of the third D trigger is connected with the positive output end Q of the second D trigger, and the outputs of the output ends Q and QN of the third D trigger are a pair of differential signals Fpre _p and Fpre _n after 4/5 double-mode frequency division. In one implementation, the D flip-flop embedded with AND gate logic comprises triodes Q1-Q20 and resistors R1-R8, wherein, The bases of the triodes Q1 and Q2 are respectively connected with the forward input end A and the reverse input end An, and the bases of the triodes Q3 and Q4 are respectively connected with the forward input end B and the reverse input end Bn; the emitters of the audions Q1 and Q2 are connected with the collector of the