CN-116133429-B - Semiconductor device and method for manufacturing the same

Abstract

The present disclosure provides a semiconductor device and a method of manufacturing the same. The semiconductor device comprises a substrate, a bit line structure, semiconductor columns, word line structures and word line structures, wherein the bit line structure is arranged on the surface of the substrate and extends along a first direction, the plurality of bit line structures are arranged along a second direction, the first direction is perpendicular to the second direction, the semiconductor columns are arranged on the surface of the bit line structure and are arranged in an array mode, the word line structure is arranged on the surface of the bit line structure and insulated from the bit line structure, the word line structure is arranged between the semiconductor columns and extends along the second direction, the plurality of word line structures and the semiconductor columns are arranged at intervals along the first direction, two adjacent semiconductor columns in the first direction share the same word line structure, and each semiconductor column is controlled by the two word line structures on two sides of the semiconductor column in the first direction. According to the technical scheme, the word line structure is arranged between the two rows of semiconductor columns, so that the arrangement of the isolation layer is reduced, the two word line structures are used for controlling the one row of semiconductor columns, and the voltage applied to the word line structure is reduced.

Inventors

• YANG DANDAN
• ZHAO LIANG
• ZENG YILEI

Assignees

• 长鑫存储技术有限公司

Dates

Publication Date

20260508

Application Date

20230207

Claims (16)

1. 1. A semiconductor device, comprising: A substrate; the bit line structures are arranged on the surface of the substrate and extend along a first direction, and a plurality of bit line structures are arranged along a second direction, and the first direction is perpendicular to the second direction; the semiconductor columns are arranged on the surface of the bit line structure and are arranged in an array manner; the word line structure is arranged on the surface of the bit line structure and insulated from the bit line structure, the word line structure is positioned between the semiconductor columns and extends along the second direction, the word line structures and the semiconductor columns are arranged at intervals along the first direction, two adjacent semiconductor columns in the first direction share the same word line structure, and each semiconductor column is controlled by the two word line structures positioned on two sides of the semiconductor column in the first direction.
2. 2. The semiconductor device of claim 1, wherein two of said word line structures on either side of said semiconductor pillar in said first direction are configured to be charged with voltages of opposite polarity.
3. 3. The semiconductor device of claim 1, wherein the bit line structure further comprises: the bit lines are arranged on the surface of the substrate, extend along the first direction and are distributed along the second direction; The bit line connection structures are arranged on the surface of the bit line, extend along the first direction, and are distributed along the second direction.
4. 4. The semiconductor device of claim 1, further comprising a first insulating layer disposed between a plurality of the bit line structures.
5. 5. The semiconductor device of claim 1, wherein the word line structure further comprises: the word lines are arranged on the surface of the bit line structure, insulated from the bit line structure, extend along a second direction and are arranged at intervals along the first direction; And the grid dielectric layer is arranged between the word line and the semiconductor column.
6. 6. The semiconductor device according to claim 1, further comprising: A second insulating layer disposed between the word line structure and the bit line structure, and between the semiconductor pillars adjacent in a second direction; The third insulating layer is arranged on the surface of the word line structure and is at least positioned between the semiconductor columns.
7. 7. The semiconductor device according to any one of claims 1 to 6, further comprising a node connection structure disposed at one end of the semiconductor pillar facing away from the bit line structure and arranged in an array.
8. 8. The semiconductor device of claim 7, further comprising a fourth insulating layer disposed on a surface of the third insulating layer at least between the node connection structures.
9. 9. The semiconductor device of claim 7, further comprising a charge storage structure arranged in an array on a surface of the node connection structure.
10. 10. A method of manufacturing a semiconductor device, comprising the steps of: Providing a substrate; Forming a bit line structure on the surface of the substrate, wherein the bit line structure extends along a first direction, a plurality of bit line structures are arranged along a second direction, and the first direction is perpendicular to the second direction; forming semiconductor columns arranged in an array on the surface of the bit line structure; And forming a word line structure on the surface of the bit line structure, wherein the word line structure is insulated from the bit line structure and is positioned between the semiconductor columns, the word line structure extends along the second direction, a plurality of word line structures and the semiconductor columns are arranged at intervals along the first direction, two adjacent semiconductor columns in the first direction share the same word line structure, and each semiconductor column is controlled by the two word line structures positioned on two sides of the semiconductor column in the first direction.
11. 11. The method of claim 10, wherein the step of forming a bit line structure on the substrate surface further comprises: forming a first conductive layer on the surface of the substrate; Etching the first conductive layer to form a first groove, wherein the first groove extends along the first direction; and forming a first insulating layer in the first groove, and taking the reserved first conductive layer as the bit line structure.
12. 12. The method of claim 10, wherein the step of forming an array of semiconductor pillars on the bit line structure surface further comprises: forming a semiconductor layer on the surface of the bit line structure; Etching the semiconductor layer to form a second groove, wherein the second groove extends along the first direction; forming a first isolation layer in the second groove; And etching the semiconductor layer and the first isolation layer to form a third groove, wherein the third groove extends along the second direction, and the etched semiconductor layer is used as the semiconductor column.
13. 13. The method of claim 12, wherein the step of forming a word line structure on the bit line structure surface further comprises: forming a second isolation layer in the third groove; Forming a gate dielectric layer, wherein the gate dielectric layer covers two sides of the semiconductor column along the first direction; Depositing conductive materials on the surface of the second isolation layer and the side surface of the gate dielectric layer to serve as word lines, wherein the gate dielectric layer and the word lines jointly form the word line structure; and forming a third insulating layer on the surfaces of the gate dielectric layer and the word line.
14. 14. The method of claim 10, wherein after the step of forming the word line structure on the bit line structure surface comprises: forming node connection structures arranged in an array on the surface of the semiconductor column; and forming an array-arranged charge storage structure on the surface of the node connection structure.
15. 15. The method of claim 14, wherein the step of forming an array of node connection structures on the semiconductor pillar surface further comprises: depositing a second conductive layer; And etching the second conductive layer to form the node connection structure in array arrangement.
16. 16. The method of claim 14, wherein prior to the step of forming an array of charge storage structures on the surface of the node connection structure, comprising: and forming a fourth insulating layer in the gap between the node connection structures.

Description

Semiconductor device and method for manufacturing the same Technical Field The present disclosure relates to the field of semiconductors, and more particularly, to a semiconductor device and a method of fabricating the same. Background With the development of integrated circuit manufacturing technology, the process nodes of integrated circuits are continuously reduced, the feature sizes of semiconductor technologies are continuously reduced, the conventional planar transistors cannot meet the requirements, and the fin transistors are generated due to operation and are widely applied. At present, a DRAM is generally a fin transistor in an array region, a Word Line (WL) is buried in a silicon substrate, so that the area of a unit transistor can be reduced, and a Bit Line (BL) and a Node Contact (NC) are located on the surface of the silicon substrate and on the same plane. However, with the shrinking of the size, the size of the bit lines and the size of the node connection structures are always mutually exclusive. And the transistor in the prior art is a word line to control the switching of a transistor, and a sufficiently high voltage needs to be provided. Therefore, how to improve the transistor wiring structure and optimize the transistor switching circuit becomes a problem to be solved at present. BRIEF SUMMARY OF THE PRESENT DISCLOSURE The technical problem to be solved by the present disclosure is how to improve the wiring structure of a transistor and optimize the switching circuit of the transistor, and to provide a semiconductor device and a method for manufacturing the same. In order to solve the problems, the present disclosure provides a semiconductor device, which comprises a substrate, a bit line structure arranged on the surface of the substrate and extending along a first direction, a plurality of bit line structures arranged along a second direction, the first direction being perpendicular to the second direction, semiconductor pillars arranged on the surface of the bit line structure and arranged in an array, and word line structures arranged on the surface of the bit line structure and insulated from the bit line structures, wherein the word line structures are positioned between the semiconductor pillars and extend along the second direction, a plurality of word line structures and the semiconductor pillars are arranged at intervals along the first direction, two adjacent semiconductor pillars in the first direction share the same word line structure, and each semiconductor pillar is controlled by two word line structures positioned on two sides of the semiconductor pillar in the first direction. In some embodiments, two of the word line structures located on both sides of the semiconductor pillar in the first direction are used to load voltages of opposite electrical polarity. In some embodiments, the bit line structure further comprises a bit line arranged on the surface of the substrate and extending along the first direction, wherein a plurality of bit lines are arranged along the second direction, and a bit line connection structure arranged on the surface of the bit line and extending along the first direction, wherein a plurality of bit line connection structures are arranged along the second direction. In some embodiments, the semiconductor device further includes a first insulating layer disposed between the plurality of bit line structures. In some embodiments, the word line structure further comprises a word line arranged on the surface of the bit line structure and insulated from the bit line structure, wherein the word line extends along a second direction, a plurality of word lines are arranged at intervals along the first direction, and a gate dielectric layer is arranged between the word line and the semiconductor column. In some embodiments, the semiconductor device further includes a second insulating layer disposed between the word line structure and the bit line structure and between the semiconductor pillars adjacent in a second direction, and a third insulating layer disposed on a surface of the word line structure and at least between the semiconductor pillars. In some embodiments, the semiconductor device further includes a node connection structure disposed at an end of the semiconductor pillar facing away from the bit line structure and arranged in an array. In some embodiments, the semiconductor device further comprises a fourth insulating layer arranged on the surface of the third insulating layer and at least positioned between the node connection structures. In some embodiments, the semiconductor device further includes a charge storage structure, and the charge storage structure is arranged on the surface of the node connection structure in an array. In order to solve the problems, the invention provides a preparation method of a semiconductor device, which comprises the steps of providing a substrate, forming a bit line structure on the surface of the subs