CN-116153377-B - Memory device, control circuit and operation method thereof

Abstract

In some aspects of the present disclosure, a memory device is disclosed. In some aspects, a memory device includes a plurality of memory cells arranged in an array, an input/output (I/O) interface connected to the plurality of memory cells to output data signals from each memory cell, and a control circuit. In some embodiments, the control circuit includes a first clock generator for generating a first clock signal and a second clock signal from an input clock signal and a Chip Enable (CE) signal and providing the first clock signal to the plurality of memory cells. In some embodiments, the control circuit includes a second clock generator for generating a third clock signal from the input clock signal and a DFT (design for testability) enable signal. In some embodiments, the control circuit generates the output clock signal from the second clock signal or the third clock signal. The embodiment of the application also provides a control circuit and an operation method thereof.

Inventors

• Xin Dayu
• Artur Cardozi

Assignees

• 台湾积体电路制造股份有限公司

Dates

Publication Date

20260508

Application Date

20220818

Priority Date

20220607

Claims (20)

1. 1. A memory device, comprising: a plurality of memory cells arranged in an array; An input/output interface connected to the plurality of memory cells to output data signals from each memory cell, and A control circuit, comprising: A first clock generator configured to generate a first clock signal and a second clock signal according to an input clock signal and a chip enable signal and to supply the first clock signal to the plurality of memory cells, and A second clock generator, different from the first clock generator, configured to generate a third clock signal from the input clock signal and to provide a design for testability enable signal to the first clock generator; wherein the control circuit generates an output clock signal according to the second clock signal or the third clock signal.
2. 2. The memory device of claim 1, wherein the control circuit performs a logical or operation on the second clock signal and the third clock signal to generate the output clock signal.
3. 3. The memory device of claim 1, wherein the design for testability enable signal is generated by performing a logical or operation on a scan enable signal and a design for testability bypass signal.
4. 4. The memory device of claim 1, wherein in response to the design for testability enable signal being in a high logic state, the memory device is in a design for testability mode and an output clock signal generated by the control circuit follows the third clock signal, Wherein an output clock signal generated by the control circuit follows the second clock signal in response to the design for testability enable signal being in a low logic state.
5. 5. The memory device of claim 1, wherein the control circuit performs a logical nor on the second clock signal and the third clock signal to generate a fourth clock signal, the fourth clock signal generating the output clock signal through an inverter.
6. 6. The memory device according to claim 1, wherein the second clock signal generates a fourth clock signal through a first inverter, the third clock signal generates a fifth clock signal through a second inverter, and the control circuit performs a logical nand on the fourth clock signal and the fifth clock signal to generate the output clock signal.
7. 7. The memory device of claim 1, wherein the second clock generator provides a buffered design for testability enable signal to the first clock generator.
8. 8. The memory device of claim 1, wherein the second clock generator generates the third clock signal from the input clock signal, the design for testability enable signal, and an initialization signal.
9. 9. The memory device of claim 1, wherein a distance between the control circuit and each of the plurality of memory cells and the input/output interface is greater than ten microns.
10. 10. A control circuit, comprising: a first clock generator for generating a task mode clock signal based on the input clock signal and the chip enable signal, and A second clock generator, different from the first clock generator, for generating a design-for-testability mode clock signal from the input clock signal and providing a design-for-testability enable signal to the first clock generator, and And the logic gate is used for generating an output clock signal according to the task mode clock signal or the testability design mode clock signal.
11. 11. The control circuit of claim 10, wherein the control circuit performs a logical or operation on the task mode clock signal and the design for testability mode clock signal to generate the output clock signal.
12. 12. The control circuit of claim 10, wherein the design for testability enable signal is generated by performing a logical or operation on a scan enable signal and a design for testability bypass signal.
13. 13. The control circuit of claim 10, wherein in response to the design for testability enable signal being in a high logic state, an output clock signal generated by the logic gate is generated from the design for testability mode clock signal, Wherein, responsive to the design for testability enable signal being a low logic state, an output clock signal generated by the logic gate is generated from the task mode clock signal.
14. 14. The control circuit of claim 10, wherein the control circuit performs a logical nor operation on the task mode clock signal and the design for testability mode clock signal to generate a first clock signal that generates the output clock signal through an inverter.
15. 15. The control circuit of claim 10, wherein the task mode clock signal generates a first clock signal through a first inverter and the design for testability mode clock signal generates a second clock signal through a second inverter, the control circuit performing a logical nand on the first clock signal and the second clock signal to generate the output clock signal.
16. 16. The control circuit of claim 10, wherein the second clock generator provides a buffered design for testability enable signal to the first clock generator.
17. 17. The control circuit of claim 10, wherein the second clock generator generates the design for testability mode clock signal from the input clock signal, the design for testability enable signal, and an initialization signal.
18. 18. The control circuit of claim 10, wherein the first clock generator generates a global clock signal from the input clock signal and the chip enable signal and provides the global clock signal to a plurality of memory cells.
19. 19. A method of operating a control circuit, comprising: receiving an input clock signal, a chip enable signal and a testability design enable signal; Generating a design for testability mode clock signal and a task mode clock signal based on the input clock signal, the chip enable signal and the design for testability enable signal, and Providing an output clock signal based on the design for testability mode clock signal or the task mode clock signal, Wherein a first clock generator receives the input clock signal and the chip enable signal to generate the task mode clock signal, The second clock generator, which is different from the first clock generator, generates the testability design mode clock signal according to the input clock signal and provides the testability design enable signal to the first clock generator.
20. 20. The method of claim 19, wherein, in response to the design for testability enable signal being in a high logic state, the output clock signal follows the design for testability mode clock signal, Wherein the output clock signal follows the task mode clock signal in response to the design for testability enable signal being in a low logic state.

Description

Memory device, control circuit and operation method thereof Technical Field Embodiments of the present application relate to a memory device, a control circuit, and a method of operating the same. Background Today's System On Chip (SOC) designs may contain a large amount of memory. These memories may occupy a large portion of the SOC, and any failure in the memories may affect the operation of the SOC. Thus, design for testability (DFT) method testing may be used to screen for damaged chips. The DFT may be implemented as a piece of circuitry on a chip, circuit board, or system for testing the circuit itself. Disclosure of Invention According to an aspect of an embodiment of the present application, there is provided a memory device including a plurality of memory cells arranged in an array, an input/output (I/O) interface connected to the plurality of memory cells to output a data signal from each of the memory cells, and a control circuit including a first clock generator to generate a first clock signal and a second clock signal according to an input clock signal and a Chip Enable (CE) signal and to provide the first clock signal to the plurality of memory cells, and a second clock generator to generate a third clock signal according to the input clock signal and a design for testability (DFT) enable (DFTEN) signal, wherein the control circuit generates the output clock signal according to the second clock signal or the third clock signal. According to another aspect of an embodiment of the present application, there is provided a control circuit including a first clock generator for generating a task mode clock (MDCK) signal from an input clock signal and a Chip Enable (CE) signal, and a second clock generator for generating a design for testability (DFT) mode clock (DDCK) signal from the input clock signal and a DFT enable (DFTEN) signal, and a logic gate for generating an output clock signal from the MDCK signal or the DDCK signal. According to yet another aspect of an embodiment of the present application, there is provided a method of operating a control circuit, including receiving an input clock signal, a chip enable signal, and a design for testability (DFT) enable (DFTEN) signal, generating a DFT mode clock (DDCK) signal and a task mode clock (MDCK) signal from the input clock signal, the chip enable signal, and the DFTEN signal, and providing an output clock signal from the DDCK signal or the MDCK signal. Drawings The various aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawings. It should be noted that the various components are not drawn to scale according to standard practice in the industry. Indeed, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Fig. 1 illustrates a block diagram of a memory system, according to some embodiments of the present disclosure. Fig. 2A-2D illustrate block diagrams of global control circuits according to some embodiments of the present disclosure. Fig. 3 illustrates a circuit diagram of a design for testability (DFT) mode clock (DDCK) generator (dft_clk) according to some embodiments of the disclosure. Fig. 4 illustrates a flow chart of a method of operating a global control circuit according to some embodiments of the present disclosure. Detailed Description The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements will be described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are in direct contact, as well as embodiments in which additional components are formed between the first component and the second component such that the first component and the second component are not in direct contact. Moreover, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, for ease of description, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise positioned (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein interpreted accordingly.