CN-116155265-B - Delay locked loop circuit and method for measuring delay of delay locked loop circuit

Abstract

A Delay Locked Loop (DLL) circuit including a delay line, a pattern injection circuit, a pattern detection circuit, and a counter is introduced. The delay line may align the phase of the reference clock signal with the phase of the feedback clock signal. The pattern injection circuit injects a predetermined pattern into the reference clock signal to generate an injection reference clock signal and sets the injection reference clock signal to the delay line. The pattern detection circuit detects a predetermined pattern in the feedback clock signal. The counter determines the delay of the delay locked loop circuit based on a first timing when the injection reference clock signal is set to the delay line and a second timing when a predetermined pattern is detected in the feedback clock signal. A method of measuring delay of a DLL circuit is also presented.

Inventors

• John Astin
• Joseph Idanza
• Fran Kaiser

Assignees

• 南亚科技股份有限公司

Dates

Publication Date

20260508

Application Date

20211222

Priority Date

20211123

Claims (20)

1. 1. A method of measuring delay of a delay locked loop circuit, comprising: Setting a reference clock signal to a delay line of the delay locked loop circuit, wherein the delay line is configured to align a phase of the reference clock signal with a phase of a feedback clock signal; Injecting a predetermined pattern into the reference clock signal to generate an injected reference clock signal; setting the injection reference clock signal to the delay line; Detecting the predetermined pattern in the feedback clock signal, and The delay of the delay locked loop circuit is determined from a first timing when the injected reference clock signal is set to the delay line and a second timing when the predetermined pattern is detected in the feedback clock signal.
2. 2. The method of claim 1, wherein injecting the predetermined pattern into the reference clock signal to generate the injected reference clock signal comprises: logic operations are performed to inject the predetermined pattern into the reference clock signal to generate the injected reference clock signal when a reset signal is set.
3. 3. The method of claim 2, wherein The predetermined pattern includes pulses that are held in a first logic state for at least one clock cycle of the reference clock signal.
4. 4. The method of claim 2, wherein The predetermined pattern includes pulses maintained in a second logic state for at least one clock cycle of the reference clock signal.
5. 5. The method of claim 2, wherein After the phase of the reference clock signal is aligned with the phase of the feedback clock signal, the injected reference clock signal is set to the delay line.
6. 6. The method of claim 2, further comprising: Delaying the reference clock signal to generate a delayed reference clock signal, and Delaying the reset signal to generate a delayed reset signal, wherein Detecting the predetermined pattern in the feedback clock signal from the delayed reference clock signal and the feedback clock signal, and The delay of the delay locked loop circuit is determined from the delayed reference clock signal and the delayed reset signal.
7. 7. The method of claim 1, wherein detecting the predetermined pattern in the feedback clock signal comprises: Detecting a pulse edge of the reference clock signal and a pulse edge of the feedback clock signal; determining misalignment of the pulse edges of the reference clock signal and the pulse edges of the feedback clock signal, and A detection signal is output in response to detecting the misalignment of the pulse edges of the reference clock signal and the pulse edges of the feedback clock signal.
8. 8. The method of claim 1, wherein determining the delay of the delay locked loop circuit based on a time period from the first timing when the injection reference clock signal is supplied to the delay line to the second timing when the predetermined pattern is detected in the feedback clock signal comprises: counting the number of clock cycles of the reference clock signal from the first timing to the second timing to obtain a count value, and Outputting the count value as the delay of the delay locked loop circuit.
9. 9. The method of claim 8, wherein counting the number of clock cycles of the reference clock signal from the first timing to the second timing comprises: Starting counting by a counter of the delay locked loop circuit at the first timing when the injection reference clock signal is set to the delay line, and At the second timing when the predetermined pattern is detected in the feedback clock signal, counting is stopped by the counter of the delay locked loop circuit.
10. 10. A delay locked loop circuit comprising: A delay line receiving a reference clock signal and generating a feedback clock signal, wherein the delay line is configured to align a phase of the reference clock signal with a phase of the feedback clock signal; A pattern injection circuit coupled to the delay line, injecting a predetermined pattern into the reference clock signal to generate an injection reference clock signal, and setting the injection reference clock signal to the delay line; a pattern detection circuit coupled to the delay line for detecting the predetermined pattern in the feedback clock signal, and A counter, coupled to the pattern detection circuit, determines a delay of the delay locked loop circuit based on a first timing when the injection reference clock signal is set to the delay line and a second timing when the predetermined pattern is detected in the feedback clock signal.
11. 11. The delay locked loop circuit of claim 10, wherein The pattern injection circuit comprises a logic circuit, and The logic circuit is configured to perform a logic operation to inject the predetermined pattern into the reference clock signal to generate the injected reference clock signal when a reset signal is set to the logic circuit.
12. 12. The delay locked loop circuit of claim 11, wherein The pattern detection circuit detects the predetermined pattern in the feedback clock signal according to the reference clock signal, and The counter determines the delay of the delay locked loop circuit from the reference clock signal and the reset signal.
13. 13. The delay locked loop circuit of claim 11, wherein The predetermined pattern is a pulse that is held in a first logic state for at least one clock cycle of the reference clock signal.
14. 14. The delay locked loop circuit of claim 11, wherein The predetermined pattern is a pulse that is held in a second logic state for at least one clock cycle of the reference clock signal.
15. 15. The delay locked loop circuit of claim 11, wherein The pattern injection circuit is configured to set the injection reference clock signal to the delay line after the phase of the reference clock signal is aligned with the phase of the feedback clock signal.
16. 16. The delay locked loop circuit of claim 11, further comprising: a signal generator generating the reset signal, wherein the signal generator includes: A first delay circuit for delaying the reference clock signal to generate a delayed reference clock signal, and A second delay circuit delays the reset signal to generate a delayed reset signal.
17. 17. The delay locked loop circuit of claim 16, wherein The pattern detection circuit detects the predetermined pattern in the feedback clock signal from the delayed reference clock signal, and The counter determines the delay of the delay locked loop circuit from the delayed reference clock signal and the delayed reset signal.
18. 18. The delay locked loop circuit of claim 10, wherein the pattern detection circuit comprises an edge detection circuit configured to: Detecting a pulse edge of the reference clock signal and a pulse edge of the feedback clock signal; determining misalignment of the pulse edges of the reference clock signal and the pulse edges of the feedback clock signal, and A detection signal is output in response to detecting the misalignment of the pulse edges of the reference clock signal and the pulse edges of the feedback clock signal.
19. 19. The delay locked loop circuit of claim 18, wherein the counter comprises: A stop signal generating circuit coupled to the pattern detecting circuit for generating a stop signal based on the detecting signal, and A counter circuit coupled to the stop signal generation circuit counts a number of clock cycles of the reference clock signal from the first timing to the second timing to obtain a count value, and outputs the count value as the delay of the delay locked loop circuit.
20. 20. The delay locked loop circuit of claim 19, wherein At the first timing when the injection reference clock signal is set to the delay line, the counter circuit begins counting, an At the second timing when the predetermined pattern is detected in the feedback clock signal, the counter circuit stops counting.

Description

Delay locked loop circuit and method for measuring delay of delay locked loop circuit Technical Field The present disclosure relates to a delay locked loop circuit, and more particularly, to a delay locked loop circuit and a method of measuring delay capable of accurately measuring delay of the delay locked loop circuit. Background A delay locked loop (delay locked loop, DLL) circuit is a circuit that provides phase alignment between an input reference clock and a clock that originates from the DLL output and is typically fed back to the DLL feedback clock input through a feedback path external to the DLL. The DLL output of the drive feedback path is a controlled buffered version of the input reference clock and the DLL circuit operates by adjusting the delay of a buffer (DLL delay line) inside the DLL until phase alignment is achieved at the DLL input. In electronic devices that include a DLL circuit, such as a memory, a key parameter that must be measured is the delay around the DLL circuit. This delay is typically designed to match the delay of elements in the signal path from the edges of the memory chip to the memory array. Using DLL circuits, these delays can be substantially removed and phase alignment can be provided between desired points in the system. It is important to accurately determine the delay of the DLL to adjust the operation of the memory. Disclosure of Invention The present disclosure describes a Delay Locked Loop (DLL) circuit and a method that can accurately measure delay around the DLL circuit. In some embodiments, the DLL circuit includes a delay line, a pattern injection circuit, a pattern detection circuit, and a counter. The delay line is configured to align a phase of the reference clock signal with a phase of the feedback clock signal. The pattern injection circuit is coupled to the delay line and configured to inject a predetermined pattern into the reference clock signal to generate an injected reference clock signal. The pattern injection circuit may set (asserts) the injection reference clock signal to the delay line. The pattern detection circuit is coupled to the delay line and configured to detect the predetermined pattern in the feedback clock signal. The counter is coupled to the pattern detection circuit and configured to determine a delay of the delay locked loop circuit from a first timing when the injection reference clock signal is set to the delay line and a second timing when the predetermined pattern is detected in the feedback clock signal. In some embodiments, the method of measuring delay of a DLL circuit includes setting a reference clock signal to a delay line of the delay locked loop circuit, wherein the delay line is configured to align a phase of the reference clock signal with a phase of a feedback clock signal, injecting a predetermined pattern into the reference clock signal to generate an injected reference clock signal, setting the injected reference clock signal to the delay line, detecting the predetermined pattern in the feedback clock signal, and determining the delay of the delay locked loop circuit based on a first timing when the injected reference clock signal is set to the delay line and a second timing when the predetermined pattern is detected in the feedback clock signal. According to embodiments of the present disclosure, measurement of the DLL delay may be performed after the delay line is calibrated and the DLL circuit is in a locked state. In this way, the measured DLL reflects the delay seen during normal operation of the DLL circuit and enables measurement of DLL delay with high accuracy. In addition, since the measurement of the DLL delay is performed based on injecting a predetermined pattern into the reference clock signal and detecting the predetermined pattern in the feedback clock signal, the measurement can be performed at any time without disturbing the system environment. Drawings FIG. 1 illustrates a schematic diagram of a Delay Locked Loop (DLL) circuit in accordance with some embodiments; FIGS. 2A and 2B illustrate timing diagrams of signals in a DLL circuit according to some embodiments; FIGS. 3A and 3B illustrate schematic diagrams of pattern injection circuits of DLL circuits according to some embodiments; FIGS. 4A-4E illustrate schematic diagrams of pattern detection circuits and timing diagrams of signals in the pattern detection circuits, according to some embodiments; FIG. 5 illustrates a schematic diagram of a counter of a DLL circuit according to some embodiments; FIG. 6 illustrates a schematic diagram of a DLL circuit according to some alternative embodiments; fig. 7 illustrates a flow chart of a method of measuring delay of a DLL circuit according to some embodiments. Detailed Description Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used through