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CN-116166475-B - Efficient data verification system and method thereof

CN116166475BCN 116166475 BCN116166475 BCN 116166475BCN-116166475-B

Abstract

An efficient data verification system and method. The efficient data verification system comprises a storage module, an io register, an io port, a comparator and an interrupt port. The io register includes a first GPIO register and a second GPIO register. The first GPIO register and the second GPIO register are used for controlling the output and the input of the io port and realizing digital-to-analog conversion, and the io port comprises a first GPIO port and a second GPIO port. The comparator is provided with two input ends which are respectively connected with the first GPIO port and the second GPIO port. The first GPIO port and the second GPIO port read the analog quantity converted by the io register and determine the level of the potential according to the analog quantity. The comparator receives high potential or low potential and compares the high potential or the low potential, the interrupt port judges whether the data are the same according to the output of the comparator, and a byte-by-byte comparison method is adopted to realize check, so that the process of temporarily storing the comparison data is omitted, meanwhile, the CRC calculation process is omitted, and the speed is faster and the efficiency is higher.

Inventors

  • JIA PENGFEI

Assignees

  • 浙江富涌电子科技有限公司

Dates

Publication Date
20260508
Application Date
20220630

Claims (9)

  1. 1. An efficient data verification method comprising the steps of: Step S1, providing two storage modules, two io registers respectively connected with the storage modules, a plurality of io ports connected with the io registers, a plurality of comparators connected with the io ports, and an interrupt port connected with the comparators, opening up two RAM areas in a RAM area of a singlechip, wherein the two RAM areas comprise a RAM1 for storing first data to be compared and a RAM2 for storing second data to be compared, parameters i1, i2, K and i1 are set in the singlechip and used for counting the number of bytes compared, i2 is used for storing the positions where different data are compared, and K is used for comparing different frequencies of statistical data; s2, determining single comparison n bytes according to the bit numbers of the first GPIO register and the second GPIO register; S3, the first GPIO register reads the RAM1 data of n bytes, then the data is transmitted to the io port after digital-to-analog conversion, the second GPIO register reads the RAM2 data of n bytes, and then the data is transmitted to the io port after digital-to-analog conversion; s4, determining the level of the potential according to the analog quantity by the io port, and then transmitting the high potential or the low potential to the comparator; Step S5, the voltages received by the two input ends of the comparator are identical and represent the same data, the comparator outputs high level, the voltages of the two input ends of the comparator are different and represent the different data, and the comparator outputs low level; Step S6, the interrupt port is a falling edge interrupt, the falling edge is interrupted when the interrupt port receives a low level, the interrupt port judges whether the interrupt occurs, the step S7 is entered when the interrupt occurs, the step S8 is entered when the interrupt does not occur, and the compared data quantity i1 is recorded when the first GPIO register and the second GPIO register transmit one byte; s7, counting different positions of the comparison data and recording the positions in the i 2; and S8, judging whether the i1 is equal to the total data, returning to the step S3 when the i1 is smaller than the total data, continuing to compare the residual data, and ending the verification when the i2 is equal to the total data.
  2. 2. The method of claim 1, wherein in step S7, according to the number of bytes being transferred in the first GPIO register and the second GPIO register, different positions of data are determined and recorded in i2, and the number of interrupts K is counted and incremented by 1 each time.
  3. 3. The method of claim 1, wherein in the step S4, the io port determines the level of the potential according to the analog quantity, 1 is high level, and 0 is low level.
  4. 4. An efficient data verification system for implementing the efficient data verification method according to any one of claims 1 to 3, wherein the efficient data verification system includes two storage modules, two io registers respectively connected with the storage modules, a plurality of io ports connected with the io registers, a plurality of comparators connected with the io ports, and an interrupt port connected with the comparators, the two storage modules respectively store first data to be compared and second data to be compared, the io registers include a first GPIO register and a second GPIO register, the first GPIO register and the second GPIO register are used for controlling the output and input of the io ports and implementing digital-to-analog conversion, the io ports include a plurality of first GPIO ports connected with the first GPIO register, and a plurality of second GPIO ports connected with the second GPIO register, the first GPIO ports and the second GPIO ports read the first GPIO ports and the second GPIO ports and read the first data to be compared with the second data to be compared, the first GPIO registers and the second GPIO registers can compare the analog potential with the second GPIO registers according to the high and low potential and the second potential, and the analog potential of the second GPIO registers can be compared with the first and the second GPIO registers and the second potential to the second potential.
  5. 5. The efficient data verification system of claim 4 wherein said first and second GPIO registers have 8 bits, 16 bits, 32 bits, 8 bits corresponding to 1byte data for simultaneous digital to analog conversion, 16 bits corresponding to 2 bytes data, 32 bits corresponding to 4 bytes data, said first and second GPIO registers having a number of bits matching said comparator number, 8 bits corresponding to 8, 16 bits corresponding to 16, 32 bits corresponding to 32.
  6. 6. The efficient data verification system of claim 5, wherein the number of the first and second GPIO ports is the same as the number of bits of the first and second GPIO registers.
  7. 7. The efficient data verification system of claim 4, wherein said comparator outputs a high level when voltages at two inputs of said comparator are identical, and outputs a low level when voltages at two inputs of said comparator are different.
  8. 8. The efficient data verification system of claim 4, wherein said comparator is further coupled to a diode, said diode preventing a signal output by said comparator from flowing backward.
  9. 9. The efficient data verification system of claim 4, wherein the interrupt port is configured as a falling edge interrupt, wherein a falling edge occurs when the comparator outputs a low level.

Description

Efficient data verification system and method thereof Technical Field The invention relates to the technical field of data verification, in particular to a high-efficiency data verification system and a method thereof. Background The electronic paper is also called digital paper. It is an ultra-thin, ultra-light display screen, i.e. understood as a thin, flexible, erasable display like paper. In the prior art, the firmware of the electronic paper module is burned through the test board. The staff needs to transmit the information of the module to be burned to the test board through the data input device, and the test board burns the information into the product, such as a firmware burning method, a firmware burning device and related equipment disclosed in patent number CN 202110997958.2. However, as different types of modules need different firmware to be downloaded into the test board, the problem that whether the firmware program is matched with the modules is involved, the problem that the firmware program is too troublesome to manually determine one by one, and the firmware is easy to make mistakes when being burned in batches, so that damaged hardware is difficult to quickly find, and the maintenance is inconvenient. In addition, in general, the verification of the recorded data is to read the recorded data for performing CRC verification after the recording is completed, so that the data needs to be read again, thereby increasing the recording time and affecting the recording efficiency. Disclosure of Invention In view of the above, the present invention provides a high-efficiency data verification system and method thereof to solve the above-mentioned technical problems. An efficient data verification system comprises two storage modules, two io registers respectively connected with the storage modules, a plurality of io ports connected with the io registers, a plurality of comparators connected with the io ports, and an interrupt port connected with the comparators. The two storage modules respectively store first data to be compared and second data to be compared. The io register comprises a first GPIO register and a second GPIO register, and the first GPIO register and the second GPIO register are used for controlling the output and the input of the io port and realizing digital-to-analog conversion. The io port comprises a plurality of first GPIO ports connected with the first GPIO registers and a plurality of second GPIO ports connected with the second GPIO registers. The first GPIO port and the second GPIO port read the analog quantity converted by the io register, determine the level of the potential according to the analog quantity, and output the high potential or the low potential to the comparator. The comparator is provided with two input ends which are respectively connected with the first GPIO port and the second GPIO port, can receive high potential or low potential and compare, and the interrupt port judges whether the data are the same according to the output of the comparator. Further, the first and second GPIO registers have 8 bits, 16 bits and 32 bits, the 8 bits correspond to 1byte data for digital-to-analog conversion at the same time, the 16 bits correspond to 2 bytes data, the 32 bits correspond to 4 bytes data, the number of bits of the first and second GPIO registers are matched with the number of the comparators, the 8 bits correspond to 8, the 16 bits correspond to 16, and the 32 bits correspond to 32. Further, the number of the first GPIO ports and the second GPIO ports is the same as the number of bits of the first GPIO registers and the second GPIO registers. Further, when voltages at two input ends of the comparator are consistent, the comparator outputs a high level if two data to be compared are identical, and when voltages at two input ends of the comparator are different, the comparator outputs a low level if two data to be compared are different. Further, the comparator is also connected with a diode, and the diode prevents the signal output by the comparator from flowing backwards. Further, the interrupt port is configured to interrupt a falling edge, and when the comparator outputs a low level, a falling edge occurs. An efficient data verification method comprising the steps of: Step S1, providing two storage modules, two io registers respectively connected with the storage modules, a plurality of io ports connected with the io registers, a plurality of comparators connected with the io ports, and an interrupt port connected with the comparators. Two RAM areas are opened up in the RAM area of the singlechip, and the RAM area comprises a RAM1 for storing first data to be compared and a RAM2 for storing second data to be compared. Parameters i1, i2, K and i1 are set in the singlechip, the number of bytes which are compared is counted, i2 is used for storing the positions where different data are compared, and K is used for counting the frequency of different data