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CN-116171042-B - Method for preparing semiconductor structure and semiconductor structure

CN116171042BCN 116171042 BCN116171042 BCN 116171042BCN-116171042-B

Abstract

The disclosure provides a method for preparing a semiconductor structure, which comprises the steps of providing a substrate, wherein the substrate comprises an active region, a first insulating part and a second insulating part, the active region is arranged between the first insulating part and the second insulating part, preparing an electric contact hole in the active region between the first insulating part and the second insulating part, and preparing a source/drain contact in the electric contact hole, wherein the source/drain contact comprises one silicon carbide sub-layer or a plurality of silicon carbide sub-layers which are sequentially overlapped, and the step of preparing each silicon carbide sub-layer comprises the steps of preparing a silicon carbide material layer in the electric contact hole, wherein the silicon carbide material layer comprises amorphous silicon carbide and crystalline silicon carbide, and removing the amorphous silicon carbide to enable the crystalline silicon carbide to be used as the silicon carbide sub-layer. The interface lattices of the silicon carbide and the active region of the active region are not matched, so that compressive stress is introduced into the source/drain contact, the mobility of carriers can be increased, and the current of the device can be further improved.

Inventors

  • CHEN XIAOXUAN

Assignees

  • 长鑫存储技术有限公司

Dates

Publication Date
20260512
Application Date
20230403

Claims (10)

  1. 1. A method for preparing a semiconductor structure is characterized in that, The method comprises the following steps: providing a substrate, wherein the substrate comprises an active region, a first insulating part and a second insulating part, and the active region is arranged between the first insulating part and the second insulating part; Etching an active region between the first insulating part and the second insulating part to form an electric contact hole, and preparing a source/drain contact in the electric contact hole, wherein the source/drain contact comprises one silicon carbide sub-layer or a plurality of silicon carbide sub-layers which are sequentially stacked; Preparing a silicon carbide material layer in the electric contact hole, wherein the silicon carbide material layer comprises amorphous silicon carbide and crystalline silicon carbide, and removing the amorphous silicon carbide to keep the crystalline silicon carbide as the silicon carbide sub-layer; The amorphous silicon carbide is attached to the side walls of the electrical contact hole and the crystalline silicon carbide is attached to the bottom wall of the electrical contact hole.
  2. 2. The method of manufacturing a semiconductor structure as claimed in claim 1, wherein, Removing the silicon carbide material layer attached to the side walls and leaving at least part of the silicon carbide material layer attached to the bottom wall in the step of removing the amorphous silicon carbide; the silicon carbide material layer further includes edge portions extending to be located on the first insulating portion and the second insulating portion, and the edge portions are also removed in the step of removing the amorphous silicon carbide.
  3. 3. The method for fabricating a semiconductor structure according to any one of claims 1 to 2, wherein, Removing the amorphous silicon carbide by adopting a dry etching mode; The etchant includes sulfur hexafluoride and oxygen.
  4. 4. The method of manufacturing a semiconductor structure according to claim 3, wherein, In the step of removing the amorphous silicon carbide, the etching selectivity of the etchant used for etching to the amorphous silicon carbide and the crystalline silicon carbide is more than or equal to 10:1.
  5. 5. The method of manufacturing a semiconductor structure according to claim 3, wherein, In the step of removing the amorphous silicon carbide, the etching time is controlled to be 1 min-10 min.
  6. 6. The method for manufacturing a semiconductor structure according to any one of claims 1 to 2 and 4 to 5, characterized in that, Preparing a silicon carbide material layer in the electric contact hole comprises controlling the thickness of the silicon carbide material layer to be 2-10 nm and/or, And controlling the total thickness of all the prepared silicon carbide sublayers to be 20-100 nm.
  7. 7. The method for manufacturing a semiconductor structure according to any one of claims 1 to 2 and 4 to 5, characterized in that, The silicon carbide material layer is prepared in the electric contact hole by an atomic layer deposition method.
  8. 8. The method for manufacturing a semiconductor structure according to any one of claims 1 to 2 and 4 to 5, characterized in that, The substrate includes a buried word line structure and a shallow trench isolation structure, the first insulating portion and the second insulating portion being each independently disposed in the buried word line structure or the shallow trench isolation structure.
  9. 9. The method for manufacturing a semiconductor structure according to any one of claims 1 to 2 and 4 to 5, characterized in that, After preparing the source/drain contacts, preparing bit lines or capacitors on the source/drain contacts that are electrically connected to the source/drain contacts.
  10. 10. The method for manufacturing a semiconductor structure according to any one of claims 1 to 2 and 4 to 5, characterized in that, The material of the first insulating part includes one or more of silicon nitride, silicon oxide and silicon oxynitride, and/or, The material of the second insulating part comprises one or more of silicon nitride, silicon oxide and silicon oxynitride, and/or, The material of the active region comprises silicon.

Description

Method for preparing semiconductor structure and semiconductor structure Technical Field The present invention relates to the field of semiconductor technology, and in particular, to a method for manufacturing a semiconductor structure and a semiconductor structure. Background With the rapid development of semiconductor memory technology, shrinking the structure size of semiconductor devices is an important direction for improving the device performance. A dynamic random access memory (DynamicRandomAccessMemory, abbreviated as DRAM) is a semiconductor device that stores and reads data using transistors and capacitors. As the size of the dynamic random access memory is reduced, the size of each part is reduced, which also causes the resistance of some key parts in the dynamic random access memory to be obviously increased, thus resulting in the reduction of the current of the device, which inevitably has a negative influence on the switching speed and even the reliability of the device. Disclosure of Invention Based on this, it is necessary to provide a method for manufacturing a semiconductor structure capable of improving the device current. According to some embodiments of the present disclosure, there is provided a method of manufacturing a semiconductor structure, the method of manufacturing a semiconductor structure including: providing a substrate, wherein the substrate comprises an active region, a first insulating part and a second insulating part, and the active region is arranged between the first insulating part and the second insulating part; Etching an active region between the first insulating part and the second insulating part to form an electric contact hole, and preparing a source/drain contact in the electric contact hole, wherein the source/drain contact comprises one silicon carbide sub-layer or a plurality of silicon carbide sub-layers which are sequentially stacked; The step of preparing each silicon carbide sub-layer comprises preparing a silicon carbide material layer in the electric contact hole, wherein the silicon carbide material layer comprises amorphous silicon carbide and crystalline silicon carbide, and removing the amorphous silicon carbide to enable the crystalline silicon carbide remained as the silicon carbide sub-layer. In some embodiments of the present disclosure, the amorphous silicon carbide is attached to a sidewall of the electrical contact hole, and the crystalline silicon carbide is attached to a bottom wall of the electrical contact hole; in the step of removing the amorphous silicon carbide, the silicon carbide material layer attached to the side wall is removed, and at least a portion of the silicon carbide material layer attached to the bottom wall remains. In some embodiments of the present disclosure, the silicon carbide material layer further includes an edge portion extending to be located on the first insulating portion and the second insulating portion, and the edge portion is further removed in the step of removing the amorphous silicon carbide. In some embodiments of the present disclosure, the amorphous silicon carbide is removed by etching. In some embodiments of the present disclosure, the etchant includes sulfur hexafluoride and oxygen. In some embodiments of the present disclosure, in the step of removing the amorphous silicon carbide, an etching selectivity of an etchant used for etching to the amorphous silicon carbide and the crystalline silicon carbide is not less than 10:1. In some embodiments of the present disclosure, in the step of removing the amorphous silicon carbide, the etching time is controlled to be 1min to 10min. In some embodiments of the present disclosure, preparing a silicon carbide material layer in the electrical contact hole includes controlling a thickness of the silicon carbide material layer to be 2 nm-10 nm. In some embodiments of the present disclosure, the total thickness of all the silicon carbide sublayers prepared is controlled to be 20 nm-100 nm. In some embodiments of the present disclosure, the manner in which the silicon carbide material layer is prepared in the electrical contact hole is an atomic layer deposition method. In some embodiments of the present disclosure, the semiconductor substrate includes a buried word line structure and a shallow trench isolation structure, the first insulating portion and the second insulating portion being each independently disposed in the buried word line structure or the shallow trench isolation structure. In some embodiments of the present disclosure, after preparing the source/drain contacts, preparing a bit line or capacitor on the source/drain contacts that is electrically connected to the source/drain contacts is further included. In some embodiments of the present disclosure, the material of the first insulating portion includes one or more of silicon nitride, silicon oxide, and silicon oxynitride. In some embodiments of the present disclosure, the material of the