CN-116187229-B - Chip fault processing method and device

CN116187229BCN 116187229 BCN116187229 BCN 116187229BCN-116187229-B

Abstract

The application provides a chip fault processing method and equipment, which comprises the steps of synthesizing an RTL code to generate a gate-level netlist, wherein the RTL code corresponds to a plurality of logic circuit units deployed on a target chip, the gate-level netlist comprises logic circuit netlists corresponding to the logic circuit units respectively, a multiplexer group associated with the logic circuit netlists is added in the gate-level netlist, under the condition that a first logic circuit unit breaks down, the modified RTL code corresponding to the first logic circuit unit is obtained, the modified RTL code is synthesized to obtain a new logic circuit netlist, the association of the logic circuit netlist corresponding to the first logic circuit unit and the corresponding first multiplexer group is canceled, and the association of the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group is established. The application can realize the quick positioning problem, quickly correct errors, improve the processing efficiency and accelerate the development progress.

Inventors

HE LU
GUO XIAOPING
NIE YINGHAO
SONG YI

Assignees

湖南胜云光电科技有限公司

Dates

Publication Date: 20260508
Application Date: 20221219

Claims (10)

1. A method for processing a chip failure, comprising: Synthesizing an RTL code to generate a gate-level netlist, wherein the RTL code corresponds to a plurality of logic circuit units deployed on a target chip, and the gate-level netlist comprises logic circuit netlists respectively corresponding to the logic circuit units; adding a multiplexer group associated with a logic circuit netlist into the gate level netlist; under the condition that a first logic circuit unit fails, acquiring a modified RTL code corresponding to the first logic circuit unit, and synthesizing the modified RTL code corresponding to the first logic circuit unit to acquire a new logic circuit netlist corresponding to the first logic circuit unit; canceling the association between the logic circuit netlist corresponding to the first logic circuit unit and the corresponding first multiplexer group, and establishing the association between the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group; Before the RTL codes are synthesized, the method further comprises the step of dividing the RTL codes into a plurality of groups of logic codes to obtain a plurality of logic circuit units, wherein each logic circuit unit corresponds to one group of logic codes.
2. The method of claim 1, wherein the logic circuit unit comprises an input section, a logic circuit section, and an output section, wherein the logic circuit netlist comprises the input section, the logic circuit section, and the output section in netlist form, and wherein the multiplexer set comprises an input multiplexer and an output multiplexer.
3. The method of claim 2, wherein adding the set of multiplexers associated with the logic circuit netlist to the gate level netlist comprises: Adding an input multiplexer and an output multiplexer of the logic circuit netlist in the gate level netlist for each logic circuit netlist; The input part and the logic circuit part of the logic circuit netlist are communicated through the input multiplexer, and the output part and the logic circuit part of the logic circuit netlist are communicated through the output multiplexer.
4. The method of claim 3, wherein the associating the new logic circuit netlist corresponding to the first logic circuit unit with the first multiplexer group comprises: The input part of the logic circuit netlist corresponding to the first logic circuit unit is communicated with the new logic circuit netlist through a first input multiplexer, and the output part of the logic circuit netlist corresponding to the first logic circuit unit is communicated with the new logic circuit netlist through a first output multiplexer; Wherein the first multiplexer group includes the first input multiplexer and the first output multiplexer.
5. The method according to any one of claims 2 to 4, wherein the synthesizing the modified RTL code corresponding to the first logic circuit unit obtains a new logic circuit netlist corresponding to the first logic circuit unit, and includes one of the following schemes: Synthesizing codes corresponding to the logic circuit parts in the modified RTL codes to obtain a new logic circuit netlist only comprising the new logic circuit parts in a netlist form; synthesizing the modified RTL codes to obtain a new logic circuit netlist comprising an input part, a new logic circuit part and an output part in a netlist form; The first multiplexer group is communicated with the input part of the logic circuit netlist corresponding to the first logic circuit unit and the new logic circuit part, and the first multiplexer group is communicated with the output part of the logic circuit netlist corresponding to the first logic circuit unit and the new logic circuit part.
6. The method of claim 5, wherein, in the case where the new logic circuit netlist includes an input portion, a new logic circuit portion, and an output portion, before establishing the association of the new logic circuit netlist corresponding to the first logic circuit unit with the first multiplexer group, the method further comprises: and extracting the new logic circuit part from the new logic circuit netlist, and adding the new logic circuit part to the logic circuit netlist corresponding to the first logic circuit unit.
7. The method of claim 5, wherein in the case where the new logic circuit netlist includes only new logic circuit portions, before establishing the association of the new logic circuit netlist corresponding to the first logic circuit unit with the first multiplexer group, the method further comprises: and directly adding the new logic circuit netlist into the logic circuit netlist corresponding to the first logic circuit unit.
8. The method of any one of claims 1 to 4, or 6 to 7, wherein the logic circuit cells form an association with a corresponding logic circuit netlist in the gate level netlist based on identification information or a keyword.
9. A method for processing a chip failure, comprising: Synthesizing an RTL code to generate a gate-level netlist, wherein the RTL code corresponds to a plurality of logic circuit units deployed on a target chip, and the gate-level netlist comprises logic circuit netlists respectively corresponding to the logic circuit units; Under the condition that a first logic circuit unit fails, adding a first multiplexer group associated with a logic circuit netlist corresponding to the first logic circuit unit into the gate-level netlist, acquiring a modified RTL code corresponding to the first logic circuit unit, and synthesizing the modified RTL code corresponding to the first logic circuit unit to acquire a new logic circuit netlist corresponding to the first logic circuit unit; canceling the association of the logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group, and establishing the association of a new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group; Before the RTL codes are synthesized, the method further comprises the step of dividing the RTL codes into a plurality of groups of logic codes to obtain a plurality of logic circuit units, wherein each logic circuit unit corresponds to one group of logic codes.
10. A computer device, comprising: a memory for storing instructions for execution by the at least one processor; a processor for executing instructions stored in a memory to perform the method of any one of claims 1 to 8 or to perform the method of claim 9.

Description

Chip fault processing method and device Technical Field The present application relates to the field of computer technologies, and in particular, to a method and an apparatus for processing a chip fault. Background In the chip design process, RTL (REGISTER TRANSFER LEVEL, register transfer layer) codes corresponding to the chip are synthesized after the design is completed to generate a gate-level netlist, and the chip is processed and generated according to the gate-level netlist. The specific flow of the chip development can be seen in fig. 1, and the time consumption of each link is calculated in weeks/months except for the development of the RTL code. If the chip is found to be defective after the later stage of chip development or after the chip is streamed back, engineering modification is required. At present, when the chip is found to have defects, RTL codes can be modified, gate-level netlists corresponding to the chip can be generated through the modified RTL codes, and the gate-level netlists can also be modified. Disclosure of Invention When engineering modification is performed by adopting a mode of modifying RTL codes, code synthesis needs to be performed again after the RTL codes are modified to modify a gate-level netlist, the synthesis needs time (for example, several days or more than ten days), if the modification can affect chip streaming time in the later stage of chip development, if the chip streaming needs to be performed again, and the development progress and the development period of the chip are affected. The modification difficulty of the gate-level netlist is high, on one hand, the readability caused by the complexity of the gate-level netlist is poor, the positioning error is difficult, and the modification is difficult after the positioning, on the other hand, the design of the back-end physical implementation is needed to be carried out again after the modification of the gate-level netlist, and a large amount of physical implementation change possibly caused by pulling a whole body is needed, and even the re-verification is needed, so that a large amount of research and development time is consumed. Therefore, the existing engineering modification mode has the problems of long time consumption, influence on development progress and difficulty in positioning and modifying errors. In view of the foregoing, embodiments of the present application provide a method, an apparatus, and a device for processing a chip failure, which overcome or at least partially solve the foregoing problems. In a first aspect, an embodiment of the present application provides a method for processing a chip fault, including: Synthesizing an RTL code to generate a gate-level netlist, wherein the RTL code corresponds to a plurality of logic circuit units deployed on a target chip, and the gate-level netlist comprises logic circuit netlists respectively corresponding to the logic circuit units; adding a multiplexer group associated with a logic circuit netlist into the gate level netlist; under the condition that a first logic circuit unit fails, acquiring a modified RTL code corresponding to the first logic circuit unit, and synthesizing the modified RTL code corresponding to the first logic circuit unit to acquire a new logic circuit netlist corresponding to the first logic circuit unit; And canceling the association of the logic circuit netlist corresponding to the first logic circuit unit and the corresponding first multiplexer group, and establishing the association of the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group. Optionally, the logic circuit unit comprises an input part, a logic circuit part and an output part, the logic circuit netlist comprises the input part, the logic circuit part and the output part in a netlist form, and the multiplexer group comprises an input multiplexer and an output multiplexer. Optionally, adding a multiplexer group associated with a logic circuit netlist in the gate level netlist includes: Adding an input multiplexer and an output multiplexer of the logic circuit netlist in the gate level netlist for each logic circuit netlist; The input part and the logic circuit part of the logic circuit netlist are communicated through the input multiplexer, and the output part and the logic circuit part of the logic circuit netlist are communicated through the output multiplexer. Optionally, the establishing the association between the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group includes: The input part of the logic circuit netlist corresponding to the first logic circuit unit is communicated with the new logic circuit netlist through a first input multiplexer, and the output part of the logic circuit netlist corresponding to the first logic circuit unit is communicated with the new logic circuit netlist through a first output multiplexer; Wherein the first mu