CN-116192121-B - A quick level shift circuit for power management chip

CN116192121BCN 116192121 BCN116192121 BCN 116192121BCN-116192121-B

Abstract

The invention discloses a rapid level shift circuit for a power management chip, which comprises a level shift core circuit and a low-delay path detection circuit. The invention adopts a resistor R1 to enable the drain voltage of a PMOS tube M5-M6 to be quickly reduced from V DDH to V SSH , improves the transient characteristic of a circuit, shortens the delay of voltage conversion and reduces switching loss, adopts a PMOS tube M13-M14 to form a pull-up MOS tube to enable the drain voltage of the PMOS tube M5-M6 to be quickly increased and reduce the switching loss, adopts a grid electrode, a source electrode and a substrate to short the NMOS tube M7-M8 to realize a diode, enables the low potential of the drain electrode of the PMOS tube M5-M6 to be not lower than V SSH -0.7, improves the reliability of the circuit, adopts an inverter to realize a delay chain technology, enables a corresponding NAND gate to output a lower pulse signal, and further enables the circuit to output a high-voltage signal consistent with the change of an input signal, thereby realizing a high-performance quick level shift circuit.

Inventors

ZHOU QIANNENG
CAO LEI
LI HONGJUAN

Assignees

重庆邮电大学

Dates

Publication Date: 20260512
Application Date: 20230103

Claims (6)

1. The quick level shift circuit for the power management chip is characterized by comprising a level shift core circuit (1) and a low-delay path detection circuit (2), wherein the signal output end of the level shift core circuit (1) is connected with the signal input end of the low-delay path detection circuit (2), and the signal output end of the low-delay path detection circuit (2) is connected with the signal input end of the level shift core circuit (1), the level shift core circuit (1) provides two control signals for the low-delay path detection circuit (2), and the low-delay path detection circuit (2) generates a high-voltage output signal at the output end; The level shift core circuit (1) includes: the input end of the inverter inv1 is connected with the circuit input end IN, the output end of the inverter inv1 is respectively connected with the grid electrode of the NMOS tube M1 and the input end of the inverter inv2, the output end of the inverter inv2 is connected with the grid electrode of the NMOS tube M2, the source electrode of the PMOS tube M5 is respectively connected with the source electrode of the PMOS tube M6, the source electrode of the PMOS tube M13, the source electrode of the PMOS tube M9, the source electrode of the PMOS tube M14, the source electrode of the PMOS tube M11 and the high-voltage domain power supply end VDDH, the grid electrode of the PMOS tube M5 is respectively connected with the drain electrode of the PMOS tube M6, the source electrode of the PMOS tube M4, the drain electrode of the NMOS tube M14, the drain electrode of the PMOS tube M8 and the grid electrode of the PMOS tube M11, the drain electrode of the PMOS tube M5 is respectively connected with the source electrode of the PMOS tube M3, the grid electrode of the PMOS tube M6, the drain electrode of the PMOS tube M13, the grid electrode of the NMOS tube M9, the grid electrode of the NMOS tube M10 and the drain electrode of the NMOS tube M7, the grid electrode of the PMOS tube M3 is respectively connected with one end of a resistor R1 and the grid electrode of the PMOS tube M4, the other end of the resistor R1 is respectively connected with the substrate of the NMOS tube M7, the source electrode of the NMOS tube M7, the grid electrode of the NMOS tube M7, the source electrode of the NMOS tube M10, the substrate of the NMOS tube M8, the source electrode of the NMOS tube M8, the grid electrode of the NMOS tube M8, the source electrode of the NMOS tube M12 and the high-voltage domain low-power end VSSH, the drain electrode of the PMOS tube M3 is connected with the drain electrode of the NMOS tube M1, the source electrode of the NMOS tube M1 is respectively connected with the source electrode of the NMOS tube M2 and the external ground wire GND, the drain electrode of the PMOS tube M4 is respectively connected with the drain electrode of the NMOS tube M2, the drain electrode of the PMOS tube M9 is respectively connected with the input end of the NMOS tube M10, the inverter inv3 and one end of the input end of the NAND1, the drain of the PMOS transistor M11 is connected to the drain of the NMOS transistor M12, the input terminal of the inverter inv6, and an input terminal of the nand gate nand2, respectively.
2. A fast level shifting circuit for a power management chip according to claim 1, wherein the low-latency path detection circuit (2) comprises: the output end of the inverter inv3 is connected with the input end of the inverter inv4, the output end of the inverter inv4 is connected with the input end of the inverter inv5, the output end of the inverter inv5 is connected with the other input end of the NAND gate nand1, the output end of the NAND gate nand1 is respectively connected with the gate of the PMOS tube M14 and one input end of the NAND gate nand3, the other input end of the NAND gate nand3 is respectively connected with the output end of the NAND gate nand4 and the output end OUT of the circuit, the output end of the NAND gate nand3 is connected with one input end of the NAND gate nand4, the output end of the inverter inv6 is connected with the input end of the inverter inv7, the output end of the inverter inv7 is connected with the other input end of the NAND gate nand 8, the other input end of the NAND gate nand2 is connected with the other input end of the PMOS tube M14, and the other input end of the NAND gate nand2 is connected with the other input end of the NAND gate nand 4.
3. The circuit of claim 1, wherein in the level shift core circuit (1), the operating voltages of the inverter inv1 and the inverter inv2 are V DD and lower than the high-voltage-domain low-power-supply terminal VSSH voltage V SSH and the high-voltage-domain power-supply terminal VDDH voltage V DDH , wherein V DDH -V SSH =5v, the nmos transistor M1, NMOS tube M2, The PMOS tube M3 and the PMOS tube M4 are large-sized high-voltage power tubes, the maximum withstand voltage between the drain and the source of the high-voltage power tubes is larger than V DDH , the resistor R1 enables the drain electrode of the PMOS tube M5, namely the node D voltage V D or the drain electrode of the PMOS tube M6, namely the node E voltage V E , to be rapidly reduced from V DDH to V SSH , the PMOS tube M13 and the PMOS tube M14 are pull-up MOS tubes, the voltage V D or the voltage V E can be rapidly increased, the grid electrode, The diode which is realized by the NMOS tube M7 and the NMOS tube M8 with the source and the substrate being IN short circuit ensures that the voltages V D and V E are not lower than V SSH -0.7, so that the voltage difference between the source and the grid of the PMOS tube M5 and the PMOS tube M6 is always smaller than the breakdown voltage thereof, the voltage difference between the source and the grid of the PMOS tube M9 and the PMOS tube M11 is always smaller than the breakdown voltage thereof, the reliability of the circuit device is ensured, when the input signal of the input end IN of the circuit is changed from 0 to V DD , the voltage V A of the drain electrode of the NMOS tube M1 is increased, the voltage V D is changed from V SSH to V DDH , the voltage V F of the drain electrode of the PMOS tube M9 is changed from V DDH to V SSH , the voltage V B of the node B is reduced to the external ground GND potential, the grid capacitor C GD4 of the large-size high-voltage power PMOS tube M4 enables the grid node C voltage V8 of the high-voltage PMOS tube M4 to be reduced, and then the voltage V E is reduced to be approximately equal to the voltage V SSH , and when the voltage V SSH is changed from V SSH to 3V SSH , and the voltage V SSH is changed from V SSH to 3V SSH .
4. A fast level shifting circuit for a power management chip as set forth in claim 3, wherein in said low-latency path detection circuit (2), an inverter inv3, an inverter inv4, an inverter inv5, an inverter inv6, an inverter inv7, an inverter inv8, a nand gate nand1, a nand gate nand2, When the input signal of the input end IN of the circuit is changed from 0 to the working power supply voltage V DD of the inverter inv1, the drain electrode of the PMOS transistor M9, namely the node F voltage V F , is changed from V DDH to V SSH by the inverter inv3, when the working power supply voltage of the nand gate nand3 and the nand gate nand4 is the voltage V DDH of the high-voltage domain power supply end VDDH and the working ground voltage is the voltage V SSH of the high-voltage domain low-power supply end VSSH, The delay chain formed by the inverter inv4 and the inverter inv5 keeps the voltage of the output end of the NAND gate nand1 as V DDH , and meanwhile, the voltage V G of the drain electrode of the PMOS tube M11, namely the node G, is changed from V SSH to V DDH , and the voltage is changed from the voltage V SSH to the voltage V DDH through the inverter inv6, The delay chain composed of the inverter inv7 and the inverter inv8 makes the output end of the NAND gate nand2 generate a down pulse signal from V DDH to V SSH with the pulse width of the inverter inv6, The delay time of the delay chain formed by the inverter inv7 and the inverter inv8 changes the voltage of the output end OUT of the circuit from V SSH to V DDH consistent with the change of the input signal of the input end IN, and similarly, when the input signal of the input end IN of the circuit changes from V DD to 0, the output end of the NAND gate nand1 generates a lower pulse signal from V DDH to V SSH , and the pulse width is that of the output end of the NAND gate nand1 is formed by the inverter inv3, The delay time of the delay chain formed by the inverter inv4 and the inverter inv5 keeps the voltage of the output end of the NAND2 at V DDH , so that the output end OUT of the circuit is changed from V DDH to V SSH , and the change of the input signal of the input end IN is consistent.
5. The rapid level shift circuit for power management chip according to claim 3 or 4, wherein when the input signal of the input terminal IN of the circuit is changed from 0 to V DD , the output terminal OUT of the circuit is also changed from V SSH to V DDH , wherein V DD is the operating power voltage of the inverter inv1, V SSH is the high-voltage domain low-power terminal VSSH voltage, and V DDH is the high-voltage domain power terminal VDDH voltage, and IN the process, the delay from the input terminal IN to the output terminal OUT is controlled by the delay time T 1 of the inverter inv1, Delay time T 2 of inverter inv2, delay time T 3 from gate of NMOS tube M2 to node E, delay time T 4 from node E to output end of NAND gate nand2, The delay time T 5 from the output end of the NAND gate nand2 to the output end OUT of the circuit is formed, wherein the delay time T 3 has the largest proportion, the transient enhancement resistor R1 and the gate-source capacitor and the gate-drain capacitor of the PMOS tube M3 and the PMOS tube M4 with large channel width-length ratio form resistance-capacitance delay, so that the voltage V C of the node C and the voltage VSSH of the low power supply end VSSH of the high voltage domain have certain delay time, the NMOS tube M2 is started, the voltage V B of the node B is rapidly reduced, the voltage V C is lower through the coupling of the gate-drain capacitor of the PMOS tube M4, the gate-source voltage |V GS4 |=|V C -V E | of the PMOS tube M4 is larger and the current I 4 working in the saturation region is larger, and the grid electrode, The diode realized by shorting the source and the substrate with the NMOS transistor M8 makes the minimum value of the voltage V E not lower than V SSH -0.7, so that the delay time T 3 =C E (V DDH -V SSH +0.7)/I 4 is reduced, and the large current I 4 can effectively reduce the delay time T 3 , wherein C E is the parasitic capacitance of the node E.
6. The fast level shift circuit for a power management chip as claimed IN claim 5, wherein when an input signal at an input terminal IN of the circuit is changed from V DD to 0, an output terminal OUT of the circuit is also changed from V DDH to V SSH , wherein V DD is an operating power supply voltage of an inverter inv1, V SSH is a high-voltage-domain low-power supply terminal VSSH voltage, and V DDH is a high-voltage-domain power supply terminal VDDH voltage, and IN the process, a delay from the input terminal IN to the output terminal OUT is mainly composed of a delay time T 1 of an inverter inv1, The delay time T 2b from the grid electrode of the NMOS tube M1 to the node D, the delay time T 3b from the node D to the output end of the NAND gate nand1, The delay time T 4b from the output end of the NAND gate nand1 to the output end OUT of the circuit is formed, wherein the delay time T 2b has the largest proportion, the transient enhancement resistor R1 and the gate-source capacitance and the gate-drain capacitance of the PMOS tube M3 and the PMOS tube M4 with large channel width-length ratio form resistance-capacitance delay, so that the voltage V C of the node C and the voltage VSSH of the low power supply end VSSH of the high voltage domain have certain delay time, the NMOS tube M1 is started, the voltage V A of the node A is rapidly reduced, the voltage V C is lower through the coupling of the gate-drain capacitance of the PMOS tube M3, the gate-source voltage |V GS3 |=|V C -V D | of the PMOS tube M3 is larger and the current I 3 working in the saturation region is larger, and the grid electrode, The diode realized by shorting the source and the substrate with the NMOS transistor M7 makes the minimum value of the voltage V D not lower than V SSH -0.7, so that the delay time T 2b =C D (V DDH -V SSH +0.7)/I 3 is reduced, and the large current I 3 can effectively reduce the delay time T 2b , wherein C D is the parasitic capacitance of the node D.

Description

A quick level shift circuit for power management chip Technical Field The invention belongs to the technical field of microelectronics, and particularly relates to a rapid level shift circuit for a power management chip. Background As power management technology has matured, power management chips have become an integral part of electronic products. The level shift circuit is used as one of the core circuits of the power management chip, and the performance of the level shift circuit directly influences the performance characteristics of the power management chip. Fig. 1 is a conventional level shift circuit, which mainly comprises a high-voltage NMOS transistor M1, a low-voltage PMOS transistor M2, a low-voltage NMOS transistor M3, a resistor R1, and a zener diode Z1. When the input terminal IN is at a high level, the NMOS transistor M1 is turned on, the drain voltage of the NMOS transistor M1 is pulled down, and the zener diode is connected IN parallel with the resistor R1 to prevent the drain voltage of the NMOS transistor M1 from being pulled down to break down the gate oxide layer of the PMOS transistor M2, and the output terminal OUT is high. When the input terminal IN is at a low level, the NMOS transistor M1 is turned off, the drain voltage of the NMOS transistor M1 is pulled high, and the output terminal OUT is low. The traditional level shift circuit has the defects of high power consumption, high delay, inconsistent rising edge delay and falling edge delay and the like, so that the application of the traditional level shift circuit in a high-precision system is limited. Disclosure of Invention The present invention is directed to solving the above problems of the prior art. A fast level shifting circuit for a power management chip is presented. The technical scheme of the invention is as follows: The quick level shift circuit for the power management chip comprises a level shift core circuit (1) and a low-delay path detection circuit (2), wherein the signal output end of the level shift core circuit (1) is connected with the signal input end of the low-delay path detection circuit (2), the signal output end of the low-delay path detection circuit (2) is connected with the signal input end of the level shift core circuit (1), the level shift core circuit (1) provides two control signals for the low-delay path detection circuit (2), and the low-delay path detection circuit (2) generates a high-voltage output signal at the output end. Further, the level shift core circuit (1) includes: the input end of the inverter inv1 is connected with the circuit input end IN, the output end of the inverter inv1 is respectively connected with the grid electrode of the NMOS tube M1 and the input end of the inverter inv2, the output end of the inverter inv2 is connected with the grid electrode of the NMOS tube M2, the source electrode of the PMOS tube M5 is respectively connected with the source electrode of the PMOS tube M6, the source electrode of the PMOS tube M13, the source electrode of the PMOS tube M9, the source electrode of the PMOS tube M14, the source electrode of the PMOS tube M11 and the high-voltage domain power supply end VDDH, the grid electrode of the PMOS tube M5 is respectively connected with the drain electrode of the PMOS tube M6, the source electrode of the PMOS tube M4, the drain electrode of the NMOS tube M14, the drain electrode of the PMOS tube M8 and the grid electrode of the PMOS tube M11, the drain electrode of the PMOS tube M5 is respectively connected with the source electrode of the PMOS tube M3, the grid electrode of the PMOS tube M6, the drain electrode of the PMOS tube M13, the grid electrode of the NMOS tube M9, the grid electrode of the NMOS tube M10 and the drain electrode of the NMOS tube M7, the grid electrode of the PMOS tube M3 is respectively connected with one end of a resistor R1 and the grid electrode of the PMOS tube M4, the other end of the resistor R1 is respectively connected with the substrate of the NMOS tube M7, the source electrode of the NMOS tube M7, the grid electrode of the NMOS tube M7, the source electrode of the NMOS tube M10, the substrate of the NMOS tube M8, the source electrode of the NMOS tube M8, the grid electrode of the NMOS tube M8, the source electrode of the NMOS tube M12 and the high-voltage domain low-power end VSSH, the drain electrode of the PMOS tube M3 is connected with the drain electrode of the NMOS tube M1, the source electrode of the NMOS tube M1 is respectively connected with the source electrode of the NMOS tube M2 and the external ground wire GND, the drain electrode of the PMOS tube M4 is respectively connected with the drain electrode of the NMOS tube M2, the drain electrode of the PMOS tube M9 is respectively connected with the input end of the NMOS tube M10, the inverter inv3 and one end of the input end of the NAND1, the drain of the PMOS transistor M11 is connected to the drain of the NMOS transistor M12, the input terminal o