CN-116208147-B - Sectional type R-2R inverted trapezoidal resistance network with high spurious-free dynamic range

CN116208147BCN 116208147 BCN116208147 BCN 116208147BCN-116208147-B

Abstract

The invention discloses a segmented R-2R inverted resistor network with high spurious-free dynamic range, which improves the spurious-free dynamic range (Spurious-FREE DYNAMIC RANGE, SFDR) of a circuit by carrying out segmented processing on the R-2R inverted resistor network and carrying out non-overlapping rotation selection processing on a high-order segment resistor network. The circuit mainly comprises a thermometer decoder, an accumulator, a logarithmic shifter, a level holding circuit, a latch, a segmented R-2R inverted ladder resistor network and a digital signal decoding circuit, wherein the thermometer decoder is used for transcoding high-order 4-bit binary codes into 15-level thermometer codes, the accumulator is used for accumulating the high-order 4-bit binary codes to generate a shift control signal (also called a pointer) required by the logarithmic shifter, the logarithmic shifter is used for carrying out shift operation according to the shift control signal input by the accumulator and the input thermometer codes, the level holding circuit is used for compensating the level lost when the digital shifter carries out shift operation, the latch is used for carrying out time domain alignment on low-order 12-bit and high-order 4-bit signals, and the segmented R-2R inverted ladder resistor network is used for receiving the digital signals of the latch and then decoding the digital signals.

Inventors

YUAN JUN
LIANG HONGYU
WU LIANGBO
ZHAO RUFA
YIN GUOHE
WANG WEI
WU HAO
WANG YUXIN
WANG YAN
LIU JIANWEI

Assignees

重庆邮电大学
中国电子科技集团公司第二十四研究所

Dates

Publication Date: 20260508
Application Date: 20221208

Claims (6)

1. A segmented R-2R inverted ladder resistance network with high spurious-free dynamic range is characterized by comprising a thermometer decoder, an accumulator, a logarithmic shifter, a level holding circuit, a latch and a segmented R-2R inverted ladder resistance network, wherein, A thermometer decoder for transcoding the high 4-bit binary code into a 15-level thermometer code; the accumulator is used for accumulating the high 4-bit binary codes and generating a shift control signal required by the logarithmic shifter; The logarithmic shifter is used for carrying out shift operation according to the shift control signal input by the accumulator and the 15-stage thermometer code input; A level holding circuit for compensating a level lost when the logarithmic shifter performs a shifting operation; a latch for time domain alignment of the low 12 and high 4 bits signals; The segmented R-2R inverted resistor network is segmented by 4+12, 4 binary codes of a high-level segment are transcoded into 15-level thermometer codes, 12 binary codes of a low-level segment are not transcoded, each branch of the high-level segment consists of two large resistors R, a small resistor R and a single-pole double-throw switch, the single-pole double-throw switch receives a signal d [ 1-15 ] for controlling the high bits, one branch of the low-level segment consists of two large resistors R and two small resistors R except one branch, the other 12 branches consist of three large resistors R, two small resistors R and a single-pole double-throw switch, and the single-pole double-throw switch receives a signal b [11:0] for controlling the low bits.
2. The segmented R-2R inverted resistor network with high spurious-free dynamic range of claim 1, wherein the thermometer decoder is configured to transcode high 4-bit binary codes into 15-level thermometer codes, and specifically comprises basic gate-level circuits such as nand gate, nor gate and nor gate, and the high 4-bit binary code D in3 D in2 D in1 D in0 is 0001, and then the transcoded thermometer code temp 15 temp 14 ……temp 1 is 000000000000001, temp 1 = The high 4-bit binary code D in3 D in2 D in1 D in0 is 0110, and the transcoded thermometer code temp 15 temp 14 ……temp 1 is 00000000011111 and temp 1 = Consists of two NAND gates and one NOT gate.
3. The high spurious-free dynamic range segmented R-2R inverse resistor network of claim 1, wherein the accumulator is composed of four full-adders and eight D-flip-flops, wherein the carry output terminal of the full-adder 1 is connected with the carry input terminal of the full-adder 2, the carry output terminal of the full-adder 2 is connected with the carry input terminal of the full-adder 3, the carry output terminal of the full-adder 3 is connected with the carry input terminal of the full-adder 4, the carry output terminal of the full-adder 4 is connected with the carry input terminal of the full-adder 1 to complete the carry-back algorithm, the output terminal S 1 ~S 4 of each full-adder reaches the D-flip-flop 1~D as the input of the D-flip-flop, the eight D-flip-flops are respectively controlled by two inverted clocks, wherein the D-flip-flop 1~D flip-flop 4 is latched, the D-flop 5~D flip-flop 8 is read, and the result p [3:0] of the D-flip-flop 5~D flip-flop 8 is returned to the full-adder input terminal B 1 ~B 4 as a control signal for shifting the temperature code.
4. The high spurious-free dynamic range segmented R-2R inverted resistor network of claim 1, wherein the logarithmic shifter is configured to perform a shift operation according to a shift control signal p [3:0] input by the accumulator and 15-level thermometer codes temp [ 1-15 ] input by the accumulator, and specifically comprises 15 x 4 muxes supporting a cyclic shift operation of a fixed bit width, each MUX comprising two NMOS switches, one NMOS switch receiving a shift control signal and the other receiving an inverse of the shift control signal.
5. The high spurious-free dynamic range segmented R-2R inverted resistor network of claim 1, wherein the level holding circuit has 15 branches, each branch is composed of two inverters and a PMOS tube, the source of the PMOS is connected to the power supply VDD, the gate is connected to the output terminal of the inverter n_1 and the input terminal of the inverter n_2 of the branch, the drain is connected to the input terminal of the inverter n_1, the shift operation is completed together with the logarithmic shifter, and the correct result is ensured.
6. The high spurious-free dynamic range segmented R-2R inverted resistor network of claim 1, wherein the latch is configured to time-domain align the low 12-bit and high 4-bit signals, and specifically comprises 12D flip-flops receiving the low 12-bit signals and 15D flip-flops receiving the high 4-bit signals after being transcoded into 15-level thermometer codes, wherein the low 12-bit signals always reach the D flip-flops first, the high 4-bit signals have a certain delay due to transcoding and algorithm, and the low 12-bit signals and the high 4-bit signals are output to the segmented R-2R inverted resistor network together after the next clock rising edge.

Description

Sectional type R-2R inverted trapezoidal resistance network with high spurious-free dynamic range Technical Field The invention belongs to the technical field of analog integrated circuit design, and particularly relates to a segmented R-2R inverted resistor network with a high spurious-free dynamic range. Background Data converters are extremely important modules in modern signal processing systems and are also bottlenecks that limit the overall system signal processing capability. The performance index of the data converter determines the quality of a product, and products with high performance are necessarily favored by consumers. In digital-to-analog converters, spurious-free dynamic range (SFDR), which refers to the ratio of the RMS amplitude of the carrier frequency (maximum signal component) to the RMS value of the sub-maximum distortion component, is an important dynamic performance parameter of data converters, is important in communication systems, such as in analog-to-digital conversion of small signals, where spurious emissions generated by a large signal path are similar to the signal path frequency, resulting in the masking of information within the small signal path. There are three design directions of voltage type, charge type and current type for the nyquist digital-to-analog converter, and SIGMA DELTA digital-to-analog converter for the oversampling digital-to-analog converter. However, for high precision digital-to-analog converters, the design choice is greatly constrained in that the voltage and charge modes are not suitable for the high precision domain due to structural reasons, so that only current mode digital-to-analog converters and SIGMA DELTA digital-to-analog converters can be selected. SIGMA DELTA digital-to-analog converters have the advantage that they can be made with high or even ultra-high precision, but they have complex digital and analog circuits, not low cost designs. In the current type digital-to-analog converter, the R-2R inverted trapezoidal resistance network is a good scheme, most of the circuits of the current type digital-to-analog converter are composed of two resistors, namely R and 2R, the matching precision is high, and meanwhile the current type digital-to-analog converter has the advantage of small area. Although the R-2R inverted resistor network can be used as a high-precision data converter, the matching precision of the actual resistor can be up to 12 bits generally, and the high-precision requirement of 16 bits is not met. Therefore, the designer proposes a R-2R inverted resistor network of a sectional scheme, which is generally divided into two or three sections, such as a 12-bit R-2R inverted resistor network, designed into (4+8) sectional type, which means that the upper 4 bits are decoded into a 15-level thermometer code, the lower 8 bits keep a binary code, then the precision requirement of the lower section only needs 8 bits, the precision requirement of the upper section needs 12 bits, the precision requirement of a 12-bit data converter is met, and all the bit sections are not required to be 12-bit precision. However, in the case of a 16-bit data converter, if the data converter is designed to be of a sectional type, a part of resistance is required to achieve 16-bit precision, so that a unit formed by an analog device cannot be completely matched, and the mismatch affects various performances of the whole converter, such as SFDR (small form factor digital error) and the like in the form of nonlinear errors. Therefore, to guarantee the performance requirements of high SFDR, designers typically choose to compensate for this mismatch in terms of switching transitions. When the high-order section switch of the segmented R-2R inverted resistor network receives a control signal, the thermometer codes used can cause the selected frequency of one part of units to be far higher than that of other parts, so that the mismatch of the parts of units can appear in a power spectrum density diagram in a harmonic mode, and the SFDR of the system is greatly reduced. Therefore, in order to optimize the phenomenon, a switching and adding algorithm in the high-order section is needed, namely an accumulator accumulates binary codes in the high-order section and takes the result as a pointer signal to control the shift operation of a logarithmic shifter on thermometer codes, and the output codes of the logarithmic shifter enable the frequency of the switch of each high-order section to be the same, so that the generation of harmonic waves is greatly inhibited, and the SFDR of the system is improved. Disclosure of Invention The present invention is directed to solving the above problems of the prior art. A segmented R-2R inverted resistor network with high spurious-free dynamic range is provided. The technical scheme of the invention is as follows: A segmented R-2R inverted ladder resistor network with high spurious-free dynamic range comprises a thermometer deco