CN-116226018-B - Data decoding structure

CN116226018BCN 116226018 BCN116226018 BCN 116226018BCN-116226018-B

Abstract

The application belongs to the technical field of data processing and discloses a data decoding structure which comprises a write control module, a read control module and a data decoding structure, wherein the write control module receives decoding data, message header indication information and effective detection information, writes the effective decoding data and the message header indication information in the decoding data into a first storage unit, the first storage unit stores the effective decoding data and the message header indication information written by the write control module, modifies the address of a write pointer of the first storage unit according to the bit width of the effective decoding data, modifies the address of a read pointer of the first storage unit according to the bit width of the read effective decoding data when the effective decoding data is read, and reads the effective decoding data with the read bit width being larger than the read bit width of the first storage unit when the bit width of the effective decoding data stored in the first storage unit is larger than the read bit width of the first storage unit.

Inventors

Gan Linghao
XUAN XUELEI

Assignees

深圳市紫光同创电子有限公司

Dates

Publication Date: 20260505
Application Date: 20230213

Claims (10)

1. The data decoding structure is characterized by comprising a write control module, a first storage unit and a read control module; the writing control module is configured to receive decoded data, header indication information and valid detection information, write valid decoded data in the decoded data and the header indication information into the first storage unit, where the header indication information is used to indicate whether the valid decoded data includes a header, and the valid detection information is used to detect the valid decoded data in the decoded data; the first memory unit is used for storing the effective decoding data and the message head indication information written by the write control module and modifying the address of the write pointer of the first memory unit according to the bit width of the effective decoding data, and For modifying an address of a read pointer of the first memory cell according to a bit width of the valid decoded data read out when the valid decoded data is read out; the read control module is configured to, when a bit width of the valid decoded data stored in the first storage unit is greater than a read bit width of the first storage unit, read the valid decoded data with a read bit width that is the read bit width.
2. The data decoding structure of claim 1, wherein the write control module, configured to receive decoded data, header indication information, and valid detection information, write valid decoded data and the header indication information in the decoded data to the first storage unit, comprises: When all the decoded data are the effective decoded data, writing the effective decoded data into the first storage unit; And when the decoded data part is the effective decoded data, writing the effective decoded data and bit supplementing data into the first storage unit, wherein the bit supplementing data is used for enabling the bit width of the data written into the first storage unit by the writing control module to be the same as the bit width of the decoded data.
3. The data decoding structure of claim 1, wherein the read control module, configured to read the valid decoded data having a bit width that is the read bit width when the bit width of the valid decoded data stored in the first memory cell is greater than the read bit width of the first memory cell, comprises: acquiring an address of a read pointer of the first storage unit and an address of a write pointer of the first storage unit, and determining a bit width of the valid decoded data stored in the first storage unit; acquiring the message header indication information written in the first storage unit, and judging whether the effective decoding data to be read out comprises the message header or not; If the valid decoded data to be read out comprises the message header, when the bit width of the valid decoded data stored in the first storage unit is larger than a first read bit width, reading the valid decoded data with the bit width being the first read bit width; and if the valid decoded data to be read does not comprise the message header, when the bit width of the valid decoded data stored in the first storage unit is larger than the second read bit width, reading the valid decoded data with the bit width being the second read bit width.
4. The data decoding structure of claim 1, further comprising: And the second storage unit is used for storing SKP data indication information, and the SKP data indication information is used for indicating whether the valid decoded data written into the first storage unit is SKP data or not.
5. The data decoding structure of claim 4, wherein the write control module further comprises: and receiving the SKP data indication information, and writing the SKP data indication information into the second storage unit.
6. The data decoding structure of claim 4, wherein the write control module further comprises: Generating decoding start instruction information, and writing the decoding start instruction information into the first storage unit and the second storage unit, wherein the decoding start instruction information is used for indicating decoding start when the write control module receives the decoding data for the first time.
7. The data decoding structure of claim 6, wherein the first storage unit further comprises: And receiving the decoding start indication information, and initializing the address of the read pointer of the first storage unit and the address of the write pointer of the first storage unit when the decoding start indication information indicates the decoding start.
8. The data decoding structure of claim 6, wherein the read control module further comprises: And generating decoding end instruction information, reading out the valid decoded data stored in the first storage unit when the decoding end instruction information indicates decoding end, and enabling the address of the read pointer of the first storage unit to be overlapped with the address of the write pointer of the first storage unit.
9. The data decoding structure of claim 4, further comprising: The SKP data control module is used for reading out the SKP data indication information written into the second storage unit when the effective decoding data read out by the read control module comprises the message header; The SKP data processing module is used for acquiring the effective decoding data read by the read control module and the SKP data indication information read by the SKP data control module, and judging whether error code data exist in the SKP data in the effective decoding data when the SKP data exist in the effective decoding data; If the SKP data in the effective decoding data has the error code data, modifying the SKP data indication information according to the error code data; and if the error code data does not exist in the effective decoding data, storing the SKP data indication information.
10. The data decoding structure of claim 9, wherein the read control module further comprises: And generating pre-reading indication information and outputting the pre-reading indication information to the SKP data control module, wherein the pre-reading indication information is used for indicating whether the read control module performs a read operation next time or not and indicating whether the effective decoding data read next time comprises the message header or not when the read control module determines that the read operation is performed next time.

Description

Data decoding structure Technical Field The application belongs to the technical field of data processing, and relates to a data decoding structure. Background The encoding/decoding of 128Bit/130Bit is a common function related to PCIE (Peripheral Component Interconnect Express) protocols, when the serdes IP (SERializer, SERializer/DESerializer, deserializer) encodes/decodes 128Bit/130Bit of transmission data, for SKP block (SKP data block) used for frequency offset compensation in the transmission data, because the SKP data block may be subjected to data addition or deletion when being transmitted from a transmitting end to a receiving end of the serdes for decoding, the Bit width of the SKP data block may be caused to have uncertainty when the data is transmitted in the serdes, and the uncertainty of the Bit width of the SKP data block may complicate the decoding process of the receiving end. The prior technical scheme for decoding the SKP data block is to limit the bit width of the SKP data block, only the bit width of the SKP data block is 64/128/192bit during decoding, and the PCIE protocol prescribes that the bit width of the SKP data block can be 64/96/128/160/192bit, when the bit width of the SKP data block is 64bit or integer multiple of 64bit, the SKP data block with the bit width of 64/128/192bit belongs to the same data block during decoding transmission data, namely the SKP data block with the bit width of 64/128/192bit always belongs to the same data block during outputting, however, the prior technical scheme solves the technical problem that the data decoding process caused by the uncertainty of the bit width of the SKP data block becomes complex, but obviously, the prior technical scheme does not support the SKP data block with the bit width of non-64 bit integer multiple, such as 96bit and 160bit, and greatly limits the application scene of the data decoding structure. Disclosure of Invention The application aims to provide a data decoding structure, which solves the technical problem that the existing data decoding structure can only support the decoding of SKP data blocks with bit widths of 64 bits and 64bit integer multiples. In order to solve the technical problems, the technical scheme of the application is as follows: The application provides a data decoding structure, which comprises a write control module, a first storage unit and a read control module; the writing control module is configured to receive decoded data, header indication information and valid detection information, write valid decoded data in the decoded data and the header indication information into the first storage unit, where the header indication information is used to indicate whether the valid decoded data includes a header, and the valid detection information is used to detect the valid decoded data in the decoded data; the first memory unit is used for storing the effective decoding data and the message head indication information written by the write control module and modifying the address of the write pointer of the first memory unit according to the bit width of the effective decoding data, and For modifying an address of a read pointer of the first memory cell according to a bit width of the valid decoded data read out when the valid decoded data is read out; the read control module is configured to, when a bit width of the valid decoded data stored in the first storage unit is greater than a read bit width of the first storage unit, read the valid decoded data with a read bit width that is the read bit width. In some embodiments, the write control module is configured to receive decoded data, header indication information, and valid detection information, write valid decoded data in the decoded data and the header indication information into the first storage unit, and includes: When all the decoded data are the effective decoded data, writing the effective decoded data into the first storage unit; And when the decoded data part is the effective decoded data, writing the effective decoded data and complementary bit data into the first storage unit, wherein the complementary bit data is used for enabling the bit width of the data written into the first storage unit to be the same as the bit width of the decoded data. In some embodiments, the read control module, configured to, when the bit width of the valid decoded data stored in the first memory cell is greater than the read bit width of the first memory cell, read the valid decoded data with a read bit width that is the read bit width, includes: acquiring an address of a read pointer of the first storage unit and an address of a write pointer of the first storage unit, and determining a bit width of the valid decoded data stored in the first storage unit; acquiring the message header indication information written in the first storage unit, and judging whether the effective decoding data to be read out comprises the message header or not; If the val