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CN-116230500-B - Method for patterning asymmetric graph

CN116230500BCN 116230500 BCN116230500 BCN 116230500BCN-116230500-B

Abstract

The invention provides a patterning method of an asymmetric pattern, which comprises the following steps of forming a first mask layer on the surface of a material layer to be etched, defining a preset symmetric pattern through the first mask layer, transferring the symmetric pattern into the material layer to be etched to form a first pattern structure, forming a second mask layer on the surface of the first pattern structure, defining the preset asymmetric pattern through the second mask layer, transferring the asymmetric pattern into the material layer to be etched to form a second pattern structure, and superposing the first pattern structure and the second pattern structure to form the asymmetric pattern structure. The invention is aimed at improving the graphic processing technology, mainly decomposing an asymmetric pattern into a symmetric pattern and an asymmetric pattern, and respectively processing the symmetric pattern and the asymmetric pattern, thereby avoiding the distortion of the pattern caused by the asymmetric pattern, improving the uniformity of the electrical property of the device, being widely applied to the active area structure of a DRAM, being characterized in that the distribution of transistor off-state currents in an array is more concentrated, and the operation window is improved.

Inventors

  • YIN XIAOMING
  • ZHOU JUN
  • HAN BAODONG

Assignees

  • 北京超弦存储器研究院

Dates

Publication Date
20260512
Application Date
20211202

Claims (9)

  1. 1. A method for patterning an asymmetric pattern, comprising the steps of: Providing a substrate; forming a layer (2) of material to be etched on a substrate; Forming a first mask layer on the surface of a material layer (2) to be etched, and defining a preset symmetrical pattern (1) through the first mask layer, wherein the first mask layer is a hard mask layer (6), and the hard mask layer (6) is provided with the symmetrical pattern (1); transferring the symmetrical pattern (1) into the material layer (2) to be etched through a first etching process to form a first pattern structure (3); forming a second mask layer on the surface of the first pattern structure (3), and defining a preset asymmetric pattern (4) through the second mask layer, wherein the second mask layer is an anti-reflection layer (7), and the anti-reflection layer (7) is provided with the asymmetric pattern (4); Transferring the asymmetric pattern (4) into the material layer (2) to be etched through a second etching process to form a second pattern structure (5); The first pattern structure (3) and the second pattern structure (5) are overlapped to form an asymmetric pattern structure.
  2. 2. A method of patterning an asymmetric pattern according to claim 1, wherein the first pattern structure (3) is a periodic line shape, a circular shape, an elliptical shape or an irregular pattern.
  3. 3. A method of patterning an asymmetric pattern according to claim 1, wherein the second pattern structure (5) is a periodic or non-periodic pattern of lines, circles, ovals or irregularities.
  4. 4. A method of patterning an asymmetric pattern as claimed in claim 1, wherein the anti-reflective layer (7) is formed by spin coating.
  5. 5. The method of claim 1, wherein the asymmetric pattern structure is an active region structure.
  6. 6. The method of claim 1, wherein the first etching process and the second etching process are performed by direct exposure, self-aligned multiple exposure, or other standardized patterning process.
  7. 7. The method according to claim 4, wherein after the anti-reflective layer (7) is formed by spin coating, the anti-reflective layer (7) is polished by chemical mechanical polishing.
  8. 8. A method of patterning an asymmetric pattern as claimed in claim 7, wherein the height of the anti-reflective layer (7) after planarization is higher than the hard mask layer (6).
  9. 9. A method of patterning an asymmetric pattern as claimed in claim 3, characterized in that the second pattern structure (5) is decomposed into a plurality of groups of asymmetric patterns (4) and the second etching process is repeated until the second pattern structure (5) is formed by superimposing the plurality of groups of asymmetric patterns (4).

Description

Method for patterning asymmetric graph Technical Field The invention relates to the technical field of semiconductor device preparation, in particular to a patterning method of an asymmetric graph. Background Currently, a main-stream DRAM product generally adopts a 6F2 device structure, wherein Active Areas (AA) are all designed to be arranged in a staggered manner to realize the most dense stacking of a final capacitor, the staggered arrangement brings challenges to a pattern processing process, due to asymmetrical pattern distribution around the active areas and unavoidable passivation effects in an etching process, fig. 7 is a top view of the active areas of 1X DRAM devices produced by three different manufacturers, white parts are active area structures, patterns are designed into uniform fins, obvious pattern distortion is finally realized on the product, fig. 8 is a cause analysis of the pattern distortion (a is a top view of a hard mask before etching, b is a pattern etching comparison of two areas of A, B, c is a top view of the etched fins), due to asymmetry of the patterns, a pattern open area at the left side of the point a forms more byproducts in the etching process, the byproducts are excessively passivated at the point a to cause the pattern distortion, the passivation is an accumulation effect, the pattern at the bottom of the active areas is obviously larger than at the top, the longitudinal plane shape of a sample is proved, and the shape is also verified to be a shape, and the current leakage current on the DRAM device is obviously influenced by the simulation result of the pattern on the fin. Therefore, the conventional pattern processing technology can lead to pattern distortion of the active region structure when processing the asymmetric pattern, the pattern distortion of the active region structure can obviously influence the electrical performance of the device, and the uniformity of the electrical performance of the device is reduced. Disclosure of Invention The invention provides a patterning method of an asymmetric pattern, which is used for solving the technical problems that the active region structure generates pattern distortion when the asymmetric pattern is processed by the existing pattern processing technology, the active region structure pattern distortion can obviously influence the electrical performance of a device, and the uniformity of the electrical performance of the device is reduced. In order to solve the technical problems, the invention discloses a patterning method of an asymmetric graph, which comprises the following steps: Providing a substrate; Forming a material layer to be etched on a substrate; forming a first mask layer on the surface of the material layer to be etched, and defining a preset symmetrical pattern through the first mask layer; Transferring the symmetrical pattern into the material layer to be etched through a first etching process to form a first pattern structure; Forming a second mask layer on the surface of the first pattern structure, and defining a preset asymmetric pattern through the second mask layer; Transferring the asymmetric pattern into the material layer to be etched through a second etching process to form a second pattern structure; The first pattern structure and the second pattern structure are overlapped to form an asymmetric pattern structure. Preferably, the first mask layer is a hard mask layer, the hard mask layer has a symmetrical pattern, the second mask layer is an anti-reflection layer, and the anti-reflection layer has an asymmetrical pattern. Preferably, the first pattern structure is a periodic line shape, a circle shape, an ellipse shape or an irregular pattern. Preferably, the second pattern structure is a periodic or aperiodic stripe, circle, ellipse or irregular pattern. Preferably, the anti-reflection layer is formed by spin coating. Preferably, the asymmetric pattern structure is an active region structure. Preferably, the first etching process and the second etching process may employ direct exposure, self-aligned multiple exposure, or other standardized patterning processes. Preferably, after the anti-reflection layer is formed by adopting a spin coating mode, the anti-reflection layer is ground by adopting a chemical mechanical polishing process. Preferably, the height of the anti-reflection layer after being ground is higher than that of the hard mask layer. Preferably, the second pattern structure is decomposed into a plurality of groups of asymmetric patterns, and the second etching process is repeated until the second pattern structure is formed by overlapping the plurality of groups of asymmetric patterns. The technical scheme of the invention has the advantages that the method for patterning the asymmetric pattern comprises the steps of providing a substrate, forming a material layer to be etched on the substrate, forming a first mask layer on the surface of the material layer to be etched, def