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CN-116230503-B - Process for improving diffusion uniformity of selective window of wafer

CN116230503BCN 116230503 BCN116230503 BCN 116230503BCN-116230503-B

Abstract

The application relates to a process for improving diffusion uniformity of a wafer selective window, which comprises the following steps of depositing a diffusion mask on the surface of a wafer, photoetching to form a diffusion window and a diffusion ring surrounding the diffusion window on the surface of the diffusion mask, and diffusing impurities in the diffusion window and the diffusion ring to form a diffusion region. According to the application, the diffusion rings are additionally arranged around the diffusion window to play an auxiliary diffusion role, and the diffusion depths of different areas of the wafer can be corrected and compensated by adjusting the positions and the sizes of the auxiliary diffusion rings of the pixels in different areas, so that the diffusion depths of impurities in each area of the wafer are nearly consistent, and the consistency of each unit of the prepared single-tube device in the wafer or the consistency of the performance of each pixel of the array chip is further improved.

Inventors

  • ZENG LEI
  • YANG JIANYAO
  • ZHANG ZHOU
  • Xiong Dailing
  • PENG XU

Assignees

  • 武汉光谷量子技术有限公司

Dates

Publication Date
20260512
Application Date
20230105

Claims (6)

  1. 1. A process for improving the diffusion uniformity of a selective window of a wafer, comprising the steps of: Depositing a diffusion mask (4) on the surface of the wafer (1); Photoetching to form a diffusion window (2) and a diffusion ring (3) surrounding the diffusion window on the surface of the diffusion mask (4); Performing impurity diffusion in the diffusion window (2) and the diffusion ring (3) to form a diffusion region (107); "photolithography to form a diffusion window (2) and a diffusion ring (3) surrounding the diffusion window on the surface of a diffusion mask (4)" specifically includes: Spin-coating photoresist on the surface of a diffusion mask (4), and sequentially performing pre-baking, exposure, development, hardening and etching procedures to form a diffusion window (2) and a diffusion ring (3) surrounding the diffusion window (2) on the surface of the diffusion mask (4); the pre-baking temperature is 95-100 ℃ and the pre-baking time is 60s; the light power of the exposure process is 12.5mw/cm 2 , and the time is 2s; development time is 20-25s; the baking temperature of the hardening process is 105-115 ℃ and the baking time is 90s.
  2. 2. A process for improving diffusion uniformity of a wafer selective window according to claim 1, characterized in that it further comprises the following steps, before diffusion of impurities in the diffusion window (2) and in the diffusion ring (3): The photoresist is removed.
  3. 3. The process for improving diffusion uniformity of a wafer selective window according to claim 1, wherein the diffusion mask (4) is a SiNx or SiO 2 dielectric film, and the growth temperature of the SiNx or SiO 2 dielectric film is 200-300 ℃.
  4. 4. The process for improving the diffusion uniformity of a wafer selective window according to claim 1, wherein the wafer (1) comprises a cap layer (101), a charge layer (102), a graded layer (103), an absorber layer (104), a buffer layer (105) and a substrate (106) in this order from top to bottom, and the diffusion region (107) is distributed in the cap layer (101).
  5. 5. Process for improving diffusion uniformity of a wafer selective window according to claim 1, characterized in that said diffusion window (2) is arranged coaxially to said diffusion ring (3).
  6. 6. The process for improving diffusion uniformity of a wafer selective window according to claim 1, wherein the diffusion is performed using a gaseous impurity source.

Description

Process for improving diffusion uniformity of selective window of wafer Technical Field The application relates to the technical field of photoelectric devices, in particular to a process for improving diffusion uniformity of a wafer selective window. Background The impurity diffusion technique is one of the important methods of forming pn junctions, and thus it is a standard fabrication process for some optoelectronic devices. In order to realize impurity diffusion, a layer of diffusion mask is usually grown on the surface of the diffused crystal, and a diffusion window is formed through the steps of photoetching, RIE etching method, photoresist removal cleaning and the like. Acceptor impurities or donor impurities diffuse into the crystal through the diffusion window to form a pn junction. For APD devices or other optoelectronic devices, pn junction depth is an important parameter that determines the magnitude of the reverse turn-on voltage Vpt and breakdown voltage Vbr of the APD device. Controlling the pn junction depth is therefore a key technique for achieving high performance optoelectronic devices. The diffusion process of the APD device or other photoelectric devices is usually completed by MOCVD, a diffusion furnace and other devices, the diffusion rate of impurities is influenced by parameters such as the surface temperature distribution of a wafer, the concentration distribution of gaseous impurities and the like, and different areas on the same wafer are influenced by the inconsistency of the parameters so as to obtain diffusion depths with different sizes, so that the uniformity of the performance of single-tube devices (or array pixels) prepared on the wafer is limited. Disclosure of Invention The embodiment of the application provides a process for improving the diffusion uniformity of a wafer selective window, which aims to solve the problem of uneven diffusion of wafer impurities in the related art. The technical scheme provided by the application is as follows: The application provides a process for improving diffusion uniformity of a wafer selective window, which comprises the following steps: depositing a diffusion mask on the surface of the wafer; photoetching to form a diffusion window and a diffusion ring surrounding the diffusion window on the surface of the diffusion mask; impurity diffusion is performed in the diffusion window and the diffusion ring to form a diffusion region. In some embodiments, "photolithography to form diffusion windows on the diffusion mask surface and diffusion rings surrounding the diffusion windows" specifically include: Spin-coating photoresist on the surface of the diffusion mask, and sequentially performing the procedures of pre-baking, exposure, development, hardening and etching to form a diffusion window and a diffusion ring surrounding the diffusion window on the surface of the diffusion mask. In some embodiments, the following steps are included before the diffusion window and diffusion ring for impurity diffusion: The photoresist is removed. In some embodiments, the diffusion mask is a SiNx or SiO 2 dielectric film, and the growth temperature of the SiNx or SiO 2 dielectric film is 200-300 ℃. In some embodiments, the wafer comprises a cap layer, a charge layer, a graded layer, an absorption layer, a buffer layer and a substrate from top to bottom, and the diffusion regions are distributed in the cap layer. In some embodiments, the diffusion window is disposed coaxially with the diffusion ring. In some embodiments, the pre-bake temperature is 95-100 ℃ for 60 seconds. In some embodiments, the exposure process has an optical power of 12.5mw/cm 2 for a period of 2 seconds. In some embodiments, the development time is 20-25s; And/or the baking temperature of the hardening process is 105-115 ℃ and the baking time is 90s. In some embodiments, the diffusion is performed using a gaseous impurity source. The technical scheme provided by the application has the beneficial effects that: According to the application, the diffusion rings are additionally arranged around the diffusion window to play an auxiliary diffusion role, and the diffusion depths of different areas of the wafer can be corrected and compensated by adjusting the positions and the sizes of the auxiliary diffusion rings of pixels in different areas, so that the diffusion depths of impurities in each area of the wafer are nearly consistent, and the performance consistency of the prepared single-tube device or array pixels is further improved. Drawings In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. FIG. 1 is