CN-116230771-B - Semiconductor device and manufacturing method thereof

CN116230771BCN 116230771 BCN116230771 BCN 116230771BCN-116230771-B

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for simplifying the manufacturing process of a three-dimensional laminated complementary transistor, reducing the manufacturing difficulty of the three-dimensional laminated complementary transistor and further being beneficial to improving the working performance of the three-dimensional laminated complementary transistor. The semiconductor device includes a semiconductor substrate, a first gate-all-around transistor, and a second gate-all-around transistor. The first gate-all-around transistor is formed on a semiconductor substrate. The first gate-all-around transistor includes a channel region of a single crystal semiconductor material. The second gate-all-around transistor is formed above the first gate-all-around transistor and is spaced apart from the first gate-all-around transistor. The second gate-all-around transistor includes a channel region of a polycrystalline semiconductor material. The second gate-all-around transistor and the first gate-all-around transistor form a three-dimensional stacked complementary transistor. The manufacturing method of the semiconductor device is used for manufacturing the semiconductor device.

Inventors

LI YONGLIANG
LIU HAOYAN
LUO JUN
WANG WENWU

Assignees

中国科学院微电子研究所

Dates

Publication Date: 20260508
Application Date: 20230330

Claims (15)

1. A semiconductor device includes a semiconductor substrate; The semiconductor device comprises a semiconductor substrate, a first gate-all-around transistor formed on the semiconductor substrate, wherein the material of a channel region included in the first gate-all-around transistor is monocrystalline semiconductor material; the first gate-all-around transistor comprises a first gate-all-around transistor, a second gate-all-around transistor, a third gate-all-around transistor, a fourth gate-all-around transistor, a fifth gate-all-around transistor and a fourth gate-all-around transistor, wherein the first gate-all-around transistor is arranged above the first gate-all-around transistor and is spaced from the first gate-all-around transistor; An interlayer dielectric layer arranged between the first gate-all-around transistor and the second gate-all-around transistor; the interlayer dielectric layer covers the first gate-all-around transistor and is used for isolating the first gate-all-around transistor from the second gate-all-around transistor; and the etching stop layer is arranged between the interlayer dielectric layer and the second ring gate transistor, and the materials of the etching stop layer and the interlayer dielectric layer are different.
2. The semiconductor device of claim 1, wherein the second gate-all-around transistor comprises a channel region having at least one layer of nanostructures, each layer of nanostructures being of unitary construction.
3. The semiconductor device of claim 1, wherein the second surrounding gate transistor includes a gate stack that is self-aligned with a channel region included in the second surrounding gate transistor.
4. The semiconductor device of claim 1, wherein the channel region comprised by the second gate-all-around transistor has at least one layer of nanostructures, each layer of the nanostructures comprising two nanowires/sheets spaced apart along a first direction; the first direction is parallel to a length direction of a gate stack structure included in the second ring gate transistor.
5. The semiconductor device of claim 4, wherein the second gate-all-around transistor comprises a channel region of an intrinsic conductivity type, or, The second gate-all-around transistor includes a channel region having a conductivity type opposite to that of the source and drain regions, and the second gate-all-around transistor includes a channel region having an impurity doping concentration that is less than that of the source and drain regions, respectively.
6. The semiconductor device according to any one of claims 1 to 5, wherein the second gate-all-around transistor comprises source, drain and channel regions of polycrystalline semiconductor material, and/or, The second gate-all-around transistor comprises a source region, a drain region and a channel region which are integrally formed.
7. A method of manufacturing a semiconductor device, comprising: providing a semiconductor substrate; forming a first gate-all-around transistor on the semiconductor substrate, wherein the material of a channel region included in the first gate-all-around transistor is monocrystalline semiconductor material; forming an interlayer dielectric layer covering the first gate-around transistor; forming an etching stop layer on the interlayer dielectric layer, wherein the etching stop layer and the interlayer dielectric layer are made of different materials; the method comprises the steps of forming a second gate-all-around transistor which is arranged above the first gate-all-around transistor and is spaced from the first gate-all-around transistor, wherein source regions, drain regions and channel regions of the second gate-all-around transistor are made of polycrystalline semiconductor materials, the second gate-all-around transistor and the first gate-all-around transistor form a three-dimensional laminated complementary transistor, and the interlayer dielectric layer is used for isolating the first gate-all-around transistor and the second gate-all-around transistor.
8. The method of manufacturing a semiconductor device according to claim 7, wherein the forming a second gate around transistor which is located above the first gate around transistor and is spaced apart from the first gate around transistor, comprises: Forming at least a pattern structure above the first gate-all-around transistor, wherein the pattern structure comprises first dielectric layers and channel forming layers which are alternately stacked along the thickness direction of the semiconductor substrate, wherein the film layer positioned at the bottom layer is the first dielectric layer in the alternately stacked first dielectric layers and channel forming layers, and each channel forming layer comprises an amorphous semiconductor layer; performing low-temperature annealing treatment on the amorphous semiconductor layer to enable the amorphous semiconductor layer to form a polycrystalline semiconductor layer; and removing at least all the first dielectric layers included in the pattern structure, so that all the polycrystalline semiconductor layers form a channel region included in the second gate-all-around transistor.
9. The method for manufacturing a semiconductor device according to claim 8, wherein each of the channel formation layers includes only the amorphous semiconductor layer.
10. The method of manufacturing a semiconductor device according to claim 9, wherein forming at least a pattern structure over the first gate-all-around transistor comprises: Forming a first dielectric material layer and an amorphous semiconductor material layer which are alternately stacked above the first gate-all-around transistor; The method comprises the steps of alternately stacking a first dielectric material layer and an amorphous semiconductor material layer, carrying out patterning treatment on the alternately stacked first dielectric material layer and amorphous semiconductor material layer to form a fin-shaped structure, wherein the fin-shaped structure is provided with a source forming region, a drain forming region and a channel forming region which is positioned between the source forming region and the drain forming region along the length direction of the fin-shaped structure, and the part of the fin-shaped structure, which is positioned in the channel forming region, is the pattern structure.
11. The method of manufacturing a semiconductor device according to claim 10, wherein after the forming of at least the pattern structure over the first gate-all-around transistor, the method further comprises, before the low-temperature annealing of the amorphous semiconductor layer: Forming a sacrificial gate and a side wall which transversely span the pattern structure, wherein the side wall is at least formed on two sides of the sacrificial gate along the length direction of the sacrificial gate; removing portions of the fin structure within the source forming region and the drain forming region; Forming a source region and a drain region which are included in the second gate-all-around transistor on two sides of the pattern structure along the length direction of the sacrificial gate; after the amorphous semiconductor layer is subjected to low-temperature annealing treatment, the manufacturing method of the semiconductor device further comprises the step of removing the sacrificial gate before at least removing all the first dielectric layers included in the pattern structure.
12. The method of manufacturing a semiconductor device according to claim 8, wherein, in the alternately stacked first dielectric layers and channel formation layers, a film layer located on a top layer is a first dielectric layer; Each channel forming layer comprises a second dielectric layer and the amorphous semiconductor layers positioned on two sides of the second dielectric layer along a first direction, wherein the material of the second dielectric layer is different from that of the first dielectric layer; And removing at least all the first dielectric layers included in the pattern structure, including removing all the first dielectric layers and all the second dielectric layers included in the pattern structure.
13. The method of manufacturing a semiconductor device according to claim 12, wherein the forming at least a pattern structure over the first gate-all-around transistor comprises: Forming the first dielectric layer and the second dielectric material layer which are alternately stacked above the first gate-all-around transistor; Selectively and transversely thinning the second dielectric material layers along the first direction so as to enable the rest part of each second dielectric material layer to form a corresponding second dielectric layer, wherein the side wall of the second dielectric layer is inwards recessed relative to the side wall of the first dielectric layer to form a channel forming space; The amorphous semiconductor material is formed to cover the semiconductor substrate, the part of the amorphous semiconductor material filled in the channel forming space is the amorphous semiconductor layer, and the part of the amorphous semiconductor material located on the first dielectric layer at the top layer is the amorphous semiconductor cover layer.
14. The method for manufacturing a semiconductor device according to claim 13, wherein the amorphous semiconductor layer is subjected to low-temperature annealing while the remaining portion of the amorphous semiconductor material forms a polycrystalline semiconductor material; after the low-temperature annealing treatment is performed on the amorphous semiconductor layer, before at least removing all the first dielectric layers included in the pattern structure, the manufacturing method of the semiconductor device further includes: doping the polycrystalline semiconductor material corresponding to the source region and the drain region of the second gate-all-around transistor to obtain the source region and the drain region of the second gate-all-around transistor; And under the mask action of a mask layer, carrying out patterning treatment on the polycrystalline semiconductor material so as to only reserve the polycrystalline semiconductor layer and a source region and a drain region included in the second gate-all-around transistor, wherein the mask layer covers the source region and the drain region included in the second gate-all-around transistor.
15. The method for manufacturing a semiconductor device according to any one of claims 8 to 14, wherein the low-temperature annealing treatment is performed at a temperature of 0 ℃ or higher and 600 ℃ or lower, and/or, The annealing time of the low-temperature annealing treatment is more than or equal to 1h and less than or equal to 24h.

Description

Semiconductor device and manufacturing method thereof Technical Field The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor device and a method for manufacturing the same. Background The three-dimensional stacked complementary transistor comprises an N-type transistor and a P-type transistor which are vertically stacked, the lateral distance between the N-type transistor and the P-type transistor is eliminated, and the effective channel width is allowed to be further increased, so that the working performance and the integration level of the semiconductor device are improved. However, the existing three-dimensional laminated complementary transistor is complicated in manufacturing process and high in processing technology requirement, so that the difficulty in manufacturing the three-dimensional laminated complementary transistor is high, and the working performance of the three-dimensional laminated complementary transistor is not improved. Disclosure of Invention The invention aims to provide a semiconductor device and a manufacturing method thereof, which are used for simplifying the manufacturing process of a three-dimensional laminated complementary transistor, reducing the manufacturing difficulty of the three-dimensional laminated complementary transistor and further being beneficial to improving the working performance of the three-dimensional laminated complementary transistor. In order to achieve the above object, in a first aspect, the present invention provides a semiconductor device including a semiconductor substrate, a first gate-all-around transistor, and a second gate-all-around transistor. The first gate-all-around transistor is formed on a semiconductor substrate. The first gate-all-around transistor includes a channel region of a single crystal semiconductor material. The second gate-all-around transistor is formed above the first gate-all-around transistor and is spaced apart from the first gate-all-around transistor. The second gate-all-around transistor includes a channel region of a polycrystalline semiconductor material. The second gate-all-around transistor and the first gate-all-around transistor form a three-dimensional stacked complementary transistor. Under the condition of adopting the technical scheme, compared with the polycrystalline semiconductor material, the monocrystalline semiconductor material has higher conductivity, so that under the condition that the channel region material in the first gate-all-around transistor included in the three-dimensional laminated complementary transistor is the monocrystalline semiconductor material, the on-resistance of the first gate-all-around transistor can be reduced, and the electrical property of the first gate-all-around transistor is improved. In addition, the material of the channel region in the second gate-all-around transistor formed above the first gate-all-around transistor is a polycrystalline semiconductor material. In this regard, in practical applications, the polycrystalline semiconductor material may be formed by depositing an amorphous semiconductor material and subjecting the amorphous semiconductor material to a low temperature annealing process. In other words, after forming at least the first gate-all-around transistor and isolating the first gate-all-around transistor from the second gate-all-around transistor, a deposition process may be used to directly form a pattern structure for manufacturing a channel region included in the second gate-all-around transistor on the interlayer dielectric layer (the pattern structure includes at least the first dielectric layer and the amorphous semiconductor layer), and a polysilicon semiconductor layer included in the channel region may be obtained through a low-temperature annealing process, so that a semiconductor substrate is bonded on the underlying first gate-all-around transistor without using an existing sequential integration manner with a complicated process, and the manufacturing difficulty of the three-dimensional stacked complementary transistor is reduced based on the semiconductor substrate to integrate the second gate-all-around transistor. And, also need not to be like the integrated mode of current monolithic (monolithic) to process the corresponding rete of manufacturing first ring gate transistor and second ring gate transistor simultaneously, aspect ratio when reducing respectively manufacturing first ring gate transistor and second ring gate transistor, and then reduce the manufacturing degree of difficulty of three-dimensional stromatolite complementary transistor. In addition, the source region and the drain region of the first gate-all-around transistor and the second gate-all-around transistor are not required to be formed by adopting multiple etching and epitaxial process shapes, so that the manufacturing process of the three-dimensional laminated complementary transistor is simplified, and t