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CN-116232513-B - Linear topology slave node synchronization method and system based on IEEE 1588 precision clock protocol

CN116232513BCN 116232513 BCN116232513 BCN 116232513BCN-116232513-B

Abstract

The invention discloses a linear topology slave node synchronization method and a system based on an IEEE 1588 precision clock protocol, wherein the method comprises the following specific steps that firstly, a slave node 1 receives a PTP message from a master node to a slave node n-1, and the PTP message is forwarded to the next stage; step two, receiving PTP message from slave node n from node 1 to slave node n-1, forwarding PTP message to upper stage, step three, averaging round trip time from node 1 to slave node n to obtain average link delay, step four, calculating master-slave clock offset according to average transmission delay, step five, and performing dynamic frequency compensation calculation. The invention can increase the synchronization precision of the system and effectively reduce the clock deviation among the nodes in the distributed system with the linear topological structure.

Inventors

  • WANG CHENGQUN
  • XU ZHUOTING
  • HAN YANCHAO

Assignees

  • 浙江理工大学

Dates

Publication Date
20260508
Application Date
20221207

Claims (6)

  1. 1. The linear topology slave node synchronization method based on the IEEE 1588 precision clock protocol is characterized by comprising the following specific steps: step one, receiving PTP messages from a master node from a node 1 to a node n-1, and forwarding the PTP messages to the next stage; step two, receiving PTP message from slave node n from node 1 to slave node n-1, forwarding PTP message to the upper stage; Step three, the average link delay is obtained by averaging the round trip time from the node 1 to the node n, and in the step, a master-slave average link delay formula is calculated as follows: In the formula (1), mean_delay 1 represents the average link Delay between the first slave node and the master node, in the formula (2), mean_delay 2 represents the average link Delay between the second slave node and the master node, in the formula (3), mean_delay n represents the average link Delay between the nth slave node and the master node, T 1 represents the timestamp of the Sync message sent by the master node device, T n is the timestamp of the Sync message received by the nth slave node, T n 3 is the timestamp of the delay_req message sent by the nth slave node, and T 4 is the timestamp of the delay_req message received by the master node device; Calculating master-slave clock offset according to the average link delay; and fifthly, performing dynamic frequency compensation calculation.
  2. 2. The method of claim 1, wherein the data forwarding from node 1 to node n in step one and step two has the same internal processing delay.
  3. 3. The method for synchronizing the slave nodes of the linear topology based on the IEEE 1588 precision clock protocol according to claim 1, wherein in the fourth step, the formula for calculating the clock offset is: In the formula (4), T n is a timestamp of receiving a Sync message by the nth slave node, T1 represents a timestamp of sending the Sync message by the master node device, and mean_delay n represents an average link delay of the nth slave node.
  4. 4. The method for synchronizing the slave nodes of the linear topology based on the IEEE 1588 precision clock protocol according to claim 3, wherein in the fifth step, the dynamic frequency compensation calculation formula is as follows: In the formula (5), MCC represents a master clock transmission interval, T2 M1 represents a time stamp of a (n+1) th transmission Sync message of the master clock, T1 M1 represents a time stamp of a (n+1) th transmission Sync message of the master clock, in the formula (6), SCC represents a time interval received from the clock, T2 S1 represents a time stamp of a (n+1) th reception Sync message of the slave clock, T1 S1 represents a time stamp of a (n+1) th reception Sync message of the slave clock, in the formula (7), MSC represents a clock deviation of the master-slave clock transmission interval, and in the formula (8), gamma represents a time ratio of the master clock to the slave clock.
  5. 5. The method of claim 4 wherein determining the value of MSC, if the highest bit is 1, indicates that the master clock frequency is higher than the slave clock frequency, then decreasing 1 for each increase in the gamma value of the ns counter of the slave clock, and conversely increasing 1 for the ns counter.
  6. 6. A system based on the method of synchronization of slave nodes of a linear topology according to any of claims 1-5, characterized in that it comprises the following modules: the data analysis module is used for analyzing the PTP message; The data forwarding module forwards the PTP message; The average link delay calculation module is used for obtaining average link delay by taking average value of round trip time from the node 1 to the node n; The clock offset calculation module calculates master-slave clock offset according to the average link delay; And the frequency compensation calculation module is used for carrying out dynamic frequency compensation calculation.

Description

Linear topology slave node synchronization method and system based on IEEE 1588 precision clock protocol Technical Field The invention belongs to the technical field of high-speed industrial Ethernet buses, and particularly relates to a linear topology slave node synchronization method and system based on an IEEE 1588 precision clock protocol. Background With the increasing application range and application scale of the distributed network, the consistency of the clocks of each distributed node in the distributed system becomes more and more important, and the accurate time synchronization technology occupies more and more important place in the distributed system, especially in the distributed system with a linear topology structure, and the topology structure can be seen in fig. 2. The clock synchronization problem arises mainly due to delay and frequency problems. The delay problem mainly comprises link delay and internal processing delay, wherein the link delay is caused by the fact that data is transmitted from a master node to a slave node and the slave node needs a certain time for transmitting the data to the slave node, the internal processing delay is mainly caused by the fact that the data needs a certain time for processing the data at the master node and the slave node, the internal processing delays of different slave nodes are unequal, and the processing delays at different moments of the same slave node also have fluctuation. The frequency problem is that since the master node and each slave node rely on their own local crystal oscillator to generate pulses, which the counter relies on to trigger counting, although these local crystals theoretically have the same frequency, in practice these individual crystals fluctuate within a small range of theoretical values, which results in a gradual divergence of the time offset between each node as the system run time becomes longer. The consequences of both of these problems may delay the data, causing greater errors in the functions of real-time control and real-time measurement. The traditional clock synchronization method mainly comprises IRIG-B codes, network Time Protocol (NTP), global Positioning System (GPS) and the like. IRIG-B code is divided into second time stamping and serial time stamping, pulse time stamping accuracy is high, but time information cannot be directly provided, and serial time stamping synchronization accuracy is not as good as pulse time stamping. And for NTP, the synchronization precision is only in millisecond level, and the method can only be applied to the occasion with low synchronization precision. The synchronization precision of the GPS can reach microsecond, but special equipment such as a GPS receiver is needed, so that the cost is high, and the realization difficulty is high. There is a need for a low cost, high precision clock synchronization method. Disclosure of Invention The invention aims to solve the problem of clock synchronization of a distributed system of a linear topological structure, and further provides a method and a system for synchronizing a linear topological slave node based on an IEEE 1588 precision clock protocol. The technical scheme adopted by the invention for solving the problems is as follows: The linear topology slave node synchronization method based on the IEEE 1588 precision clock protocol comprises the following specific steps: step one, the slave node 1 to the slave node n-1 receive the PTP message from the master node and forward the PTP message to the next stage. Step two, the slave node 1 receives the PTP message from the slave node n-1, and forwards the PTP message to the upper stage. And step three, averaging the round trip time from the node 1 to the node n to obtain the average link delay. And step four, calculating the master-slave clock offset according to the average transmission delay. And fifthly, performing dynamic frequency compensation calculation. Further, in the first and second steps, the data forwarding modules from the node 1 to the slave node n-1 have the same internal processing delay. In the third step, a master-slave average link delay formula is calculated as follows: In the formula (1), mean_delay 1 represents the average link delay between the first slave node and the master node, in the formula (2), mean_delay 2 represents the average link delay between the second slave node and the master node, and in the formula (3), mean_delay n represents the average link delay between the nth slave node and the master node. T 1 represents the timestamp of the Sync message sent by the master node device, T n is the timestamp of the Sync message received by the nth slave node, T n 3 is the timestamp of the Delay_req message sent by the nth slave node, and T 4 is the timestamp of the Delay_req message received by the master node device. Further, in the fourth step, the formula for calculating the clock offset is: Offset=Tn2-T1-Mean_delay n (4) In the formula (4), T