CN-116247001-B - Method for manufacturing through hole

Abstract

Embodiments of the present disclosure relate to a via manufacturing method. A method for fabricating an insulated conductive via is presented. The via passes through the first stack of layers to the first layer. A first cavity is formed that extends partially into the first stack of layers. A second stack of layers is formed over the first stack of layers and in the first cavity. The second stack of layers includes an etch stop layer and an insulating layer. A second cavity is then formed that extends completely through the stack of first layers and the stack of second layers to the first layers. The insulating sleeve then covers the walls and bottom of the second cavity. The insulating liner is then anisotropically etched and the second cavity is filled with a conductive material forming the core of the via.

Inventors

• M. Balas
• P. Gouraud

Assignees

• 意法半导体(克洛尔2)公司

Dates

Publication Date

20260505

Application Date

20221206

Priority Date

20220110

Claims (18)

1. 1.A method of manufacture, comprising: a) Forming a first cavity in a first stack of layers, wherein the first stack of layers includes at least one conductive or semiconductor layer and a first layer, the first cavity in the first stack of layers partially passing through the at least one conductive or semiconductor layer; b) Forming a second stack of layers on an upper surface of the first stack of layers and on walls and a bottom of the first cavity, the second stack of layers comprising an etch stop layer covered with a first insulating layer; c) Etching a second cavity through the first stack of layers and the second stack of layers, the second cavity extending between a bottom of the first cavity and the first layer; d) Forming a second insulating layer covering the second stack of layers and the walls and bottom of the second cavity; e) Anisotropically etching the second insulating layer to form an insulating sheath on the walls of the second cavity, wherein the anisotropically etching selectively etches the material of the second insulating layer over the material of the etch stop layer, and F) The second cavity is filled with a conductive material to form a conductive core through the first stack of layers to an insulated conductive via of the first layer.
2. 2. The method of claim 1, wherein step f) further comprises filling the first cavity with a conductive material.
3. 3. The method of claim 1, wherein the first layer is made of a conductive material or a semiconductor material.
4. 4. The method of claim 1, wherein step c) includes lithographically defining the location of the second cavity prior to etching.
5. 5. The method of claim 1, wherein a material of the first insulating layer and a material of the second insulating layer are selectively etchable over the material of the first layer.
6. 6. The method of claim 1, wherein the first insulating layer and the second insulating layer are made of silicon oxide, and wherein the at least one conductive or semiconductor layer is made of silicon.
7. 7. The method of claim 1, further comprising removing the etch stop layer between step e) and step f).
8. 8. The method of claim 1, wherein the etch stop layer is made of a material that can be selectively etched over a material of the first layer.
9. 9. The method of claim 1, wherein the etch stop layer is made of amorphous carbon.
10. 10. The method of claim 1, wherein the first stack of layers has a thickness greater than or equal to 6 μιη.
11. 11. The method of claim 1, wherein the first stack of layers comprises at least one insulating layer between the first layer and the at least one conductive or semiconductor layer.
12. 12. The method of claim 1, wherein the second stack comprises another insulating layer between the etch stop layer and the first stack.
13. 13. The method of claim 12, wherein a material of the etch stop layer is selectively etchable over the another insulating layer.
14. 14. The method of claim 1, wherein the first stack of layers comprises at least one layer made of an insulating material or made of a conductive or semiconductor material, the at least one layer being located between the at least one conductive or semiconductor layer and the second stack of layers.
15. 15. A method of fabricating an insulated conductive via, comprising: forming a first stack of layers on a substrate conductive or semiconductor layer, the first stack of layers comprising a conductive or semiconductor layer; Forming a first cavity of the conductive or semiconductor layer extending partially through the first stack of layers; forming a second stack of layers over the first stack of layers and in the first cavity; Wherein the second stack of layers includes an etch stop layer covered with an insulating layer; forming a mask over the insulating layer of the second stack of layers, the mask having an opening aligned with the first cavity but having a smaller dimension than the first cavity; Etching a second cavity using the opening in the mask, the second cavity extending completely through the second stack of layers and further extending completely through a remaining portion of the conductive or semiconductor layer of the first stack of layers to reach the base conductive or semiconductor layer; conformally depositing an insulating liner within the second cavity; anisotropically etching the insulating liner, wherein the anisotropically etching selectively etches the material of the insulating liner over the material of the etch stop layer, and The second cavity is filled with a conductive core.
16. 16. The method of claim 15, further comprising removing the etch stop layer of the second stack of layers after anisotropic etching and before filling the second cavity.
17. 17. The method of claim 15, wherein the etch stop layer is made of a material that can be selectively etched over the substrate conductive or semiconductor layer.
18. 18. The method of claim 15, wherein the etch stop layer is made of amorphous carbon.

Description

Method for manufacturing through hole Cross Reference to Related Applications The present application claims priority from greek patent application No.20210100851, filed on 7 at 12 at 2021, and from french patent application No.2200140, filed on 10 at 1 at 2022, the entire contents of which are incorporated herein by reference to the fullest extent permitted by law. Technical Field The present disclosure relates generally to electronic devices and methods of making the same, and more particularly, to vias and methods of making the same. Background The fabrication of vias, particularly conductive vias, is an element that exists in most electronic device fabrication processes. Electronic devices have increasingly smaller dimensions. This requires smaller vias and thus more accurate manufacturing methods. There is a need in the art for all or part of the disadvantages of known via fabrication methods. Disclosure of Invention In one embodiment, a method for fabricating an insulated conductive via through a first stack of layers to a first layer is presented. The first stack comprises at least a second conductive or semiconductor layer. The method includes a) forming a first cavity in the first stack, the first cavity partially passing through the second layer, b) forming a second stack including a third etch stop layer on an upper surface of the first stack and covered with a fourth insulating layer on a wall and a bottom of the first cavity, c) etching a second cavity through the first and second stacks, the second cavity extending between the bottom of the first cavity and the first layer, d) forming a fifth insulating layer covering the second stack and the wall and bottom of the second cavity, e) anisotropically etching the fifth layer to form an insulating jacket of the via on the wall of the second cavity, the etching being selectively etching material of the fifth layer on material of the third layer, and f) filling the second cavity with a conductive material to form a conductive core of the via. According to one embodiment, step f) further comprises filling the first cavity with a conductive material. According to an embodiment, the first layer is made of a conductive material or a semiconductor material. According to an embodiment, step c) comprises photolithography. According to an embodiment, the material of the fourth layer and the material of the fifth layer can be selectively etched on the material of the first layer. According to one embodiment, the fourth and fifth layers are made of silicon oxide and the second layer is made of silicon. According to an embodiment, the method comprises a step of removing the third layer between steps e) and f). According to an embodiment, the third layer is made of a material that is selectively etchable on the material of the first layer. According to one embodiment, the third layer is made of amorphous carbon. According to an embodiment, the first stack has a thickness of greater than or equal to 6 μm. According to an embodiment, the first stack comprises at least one sixth layer made of an insulating material between the first layer and the second layer. According to one embodiment, the second stack comprises a seventh layer made of insulating material between the third layer and the first stack. According to an embodiment, the material of the third layer can be selectively etched on the seventh layer. According to one embodiment, the first stack comprises at least one eighth layer located between the second layer and the second stack. Drawings The foregoing and other features and advantages will be described in detail in the remainder of the disclosure of the specific embodiments presented by way of illustration and not limitation with reference to the accompanying drawings wherein: Fig. 1 to 8 show steps of a via manufacturing method. Detailed Description Like features are denoted by like reference numerals throughout the various figures. In particular, structural and/or functional features common in the various embodiments may have the same reference numerals and may be provided with the same structural, dimensional, and material characteristics. For clarity, only the steps and elements useful for understanding the embodiments described herein are shown and described in detail. Unless otherwise indicated, when referring to two elements being connected together, this means that there is no direct connection of any intermediate element other than a conductor, and when referring to two elements being connected together, this means that the two elements may be connected or they may be coupled via one or more other elements. In the following disclosure, unless otherwise indicated, when referring to absolute positional qualifiers, such as the terms "front", "rear", "top", "bottom", "left", "right", etc., or when referring to relative positional qualifiers, such as the terms "upper", "lower", etc., or when referring to orientation qualifiers, such as "horizontal