CN-116258116-B - Standard cell layout optimization method, device, system and medium

CN116258116BCN 116258116 BCN116258116 BCN 116258116BCN-116258116-B

Abstract

The application provides a standard cell layout optimization method, a standard cell layout optimization device, a standard cell layout optimization system and a standard cell layout optimization medium, which are used for performing electrical simulation according to the actual technological process and structural parameters of an initial standard cell layout, and calculating simulation performance indexes of the initial standard cell layout according to simulation results; when the simulation performance index is consistent with the preset performance index, a layout dependent effect polynomial model is established according to a layout dependent effect model fitting factor of the initial standard unit layout, the structural parameters of the initial standard unit layout are corrected to obtain corrected device structural parameters, a compact model is established, and the initial standard unit layout is optimized by adopting a greedy algorithm. The semiconductor process and the device simulation tool are utilized to model based on layout dependent effects, the cost of testing flow pieces is reduced, an optimized standard unit layout is quickly generated by generating a compact model and combining a greedy algorithm, the optimization efficiency of the standard unit layout is improved, the process development is guided to be early improved, the performance of the standard unit layout is improved, and the research and development period is shortened.

Inventors

LU RENJIE
CHEN LAN

Assignees

中国科学院微电子研究所

Dates

Publication Date: 20260505
Application Date: 20230317

Claims (8)

1. The standard cell layout optimization method is characterized by comprising the following steps of: performing device electrical simulation according to the actual technological process and structural parameters of the current device initial standard unit layout to obtain a simulation result; Calculating the simulation performance index of the initial standard unit layout of the current device according to the simulation result; When the simulation performance index is consistent with a preset performance index, establishing a layout dependent effect polynomial model according to a layout dependent effect model fitting factor of the current device initial standard unit layout; Correcting the structural parameters of the initial standard unit layout of the current device according to the layout dependent effect polynomial model to obtain corrected device structural parameters; Establishing a compact model of the current device according to the modified device structure parameters; optimizing the initial standard unit layout of the current device by adopting a greedy algorithm according to the compact model of the current device to obtain an optimized standard unit layout; the method for optimizing the initial standard cell layout of the current device by adopting a greedy algorithm to obtain an optimized standard cell layout comprises the following steps: And optimizing a layout dependency factor of the layout dependency effect of the initial standard cell layout of the current device by adopting the greedy algorithm according to the layout dependency effect of the initial standard cell layout to obtain the optimized standard cell layout, wherein the layout dependency factor comprises the distances SA and SB from a Poly silicon channel to an STI, a Poly width L and a device width W.
2. The method as recited in claim 1, further comprising: Establishing a test circuit to obtain the performance, power consumption and area of the optimized standard cell layout; And when the performance of the optimized standard cell layout is larger than or equal to a first preset value, the power consumption is smaller than or equal to a second preset value and the area is smaller than or equal to a third preset value, the optimized standard cell layout is used as a final standard cell layout.
3. The method of any of claims 1-2, wherein the current device comprises a finfet device and the layout-dependent effect model fitting factors comprise fin width, fin pitch, and fin number.
4. A standard cell layout optimizing apparatus, comprising: The simulation unit is used for performing device electrical simulation according to the actual technological process and structural parameters of the current device initial standard unit layout to obtain a simulation result; The calculating unit is used for calculating the simulation performance index of the current device initial standard unit layout according to the simulation result; The establishing unit is used for establishing a layout dependent effect polynomial model according to the layout dependent effect model fitting factor of the current device initial standard unit layout when the simulation performance index is consistent with a preset performance index; The correction unit is used for correcting the structural parameters of the initial standard unit layout of the current device according to the layout dependent effect polynomial model to obtain corrected device structural parameters; the model unit is used for establishing a compact model of the current device according to the modified device structure parameters; The optimizing unit is used for optimizing the initial standard unit layout of the current device by adopting a greedy algorithm according to the compact model of the current device to obtain an optimized standard unit layout; the optimizing unit is specifically configured to: And optimizing a layout dependency factor of the layout dependency effect of the initial standard cell layout of the current device by adopting the greedy algorithm according to the layout dependency effect of the initial standard cell layout to obtain the optimized standard cell layout, wherein the layout dependency factor comprises the distances SA and SB from a Poly silicon channel to an STI, a Poly width L and a device width W.
5. The apparatus as recited in claim 4, further comprising: The test unit is used for establishing a test circuit to obtain the performance, the power consumption and the area of the optimized standard unit layout; And the comparison unit is used for taking the optimized standard cell layout as a final standard cell layout when the performance of the optimized standard cell layout is larger than or equal to a first preset value, the power consumption is smaller than or equal to a second preset value and the area is smaller than or equal to a third preset value.
6. The apparatus of any of claims 4-5, wherein the current device comprises a finfet device and the layout-dependent effect model fitting factors comprise fin width, fin pitch, and fin number.
7. A standard cell layout optimization system, comprising: A memory for storing a computer program; a processor for implementing the steps of the standard cell layout optimization method according to any one of claims 1-3 when executing said computer program.
8. A computer readable medium, characterized in that it has stored thereon a computer program which, when processed and executed, implements the steps of the standard cell layout optimization method according to any of claims 1-3.

Description

Standard cell layout optimization method, device, system and medium Technical Field The present application relates to the field of integrated circuit design, and in particular, to a method, apparatus, system, and medium for optimizing standard cell layout. Background The standard cell library is the core of the digital circuit design, and after logic synthesis is carried out on the digital circuit, the standard cell layout is integrated through a layout and wiring algorithm, so that the complexity and manufacturing risk of the circuit layout design are reduced. To improve the circuit performance of the chip, performing multiple iterative optimization on the standard cell library is an important working content for developing a PDK (Process DESIGN KIT ). In various standard unit optimization techniques, the layout dependence effect is adopted to perform standard unit layout optimization, so that the standard unit can reach the result of optimal performance and minimum process fluctuation. As the size of integrated circuit devices is continuously reduced, the fluctuation of device characteristics caused by layout change becomes more serious, resulting in deviation of actual device performance and simulation results, and perfecting layout dependent effect modeling has become an indispensable part of integrated circuit design. At 22nm and above, a Fin Field effect transistor (FinFET, fin Field-Effect Transistor) is generally adopted in a semiconductor device structure, the three-dimensional effect of the FinFET greatly increases the complexity of modeling of a Layout dependent effect, and a new process brings a new Layout dependent effect, so that the influence of LDE (Layout DEPENDENT EFFECT) on the performance of the device reaches about 30%. The layout dependence modeling is an effective method for predicting the performance change of the layout on the device, the traditional layout dependence effect modeling flow needs to test the layout design and mask flow test through LDE, iteration is repeated for a plurality of times, the flow test cost of the prior process node is higher, and the research and development period is longer. Therefore, how to improve the performance of the standard unit layout as much as possible in the early stage of process development, reduce the cost and shorten the development period is a technical problem to be solved in the field. Disclosure of Invention In view of the above, this summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. The application aims to provide a standard unit layout optimization method, device, system and medium, which can reduce test flow sheet cost, improve standard unit layout optimization efficiency, guide process development to improve standard unit layout performance in early stage and shorten research and development period. In order to achieve the above purpose, the application has the following technical scheme: in a first aspect, an embodiment of the present application provides a standard cell layout optimization method, including: performing device electrical simulation according to the actual technological process and structural parameters of the current device initial standard unit layout to obtain a simulation result; Calculating the simulation performance index of the initial standard unit layout of the current device according to the simulation result; When the simulation performance index is consistent with a preset performance index, establishing a layout dependent effect polynomial model according to a layout dependent effect model fitting factor of the current device initial standard unit layout; Correcting the structural parameters of the initial standard unit layout of the current device according to the layout dependent effect polynomial model to obtain corrected device structural parameters; Establishing a compact model of the current device according to the modified device structure parameters; And optimizing the initial standard unit layout of the current device by adopting a greedy algorithm according to the compact model of the current device to obtain an optimized standard unit layout. In one possible implementation manner, the optimizing the initial standard cell layout of the current device by adopting a greedy algorithm to obtain an optimized standard cell layout includes: And optimizing the layout dependency factor of the layout dependency effect of the initial standard unit layout of the current device by adopting the greedy algorithm according to the layout dependency effect of the initial standard unit layout, so as to obtain the optimized standard unit layout. In one possible implementation, the method further includes: Establishing a test circuit to ob